artiq/examples/compiler_test.py

42 lines
1.1 KiB
Python
Raw Normal View History

2014-05-31 00:20:13 +08:00
from artiq.language.units import *
from artiq.language.core import *
2014-05-31 00:20:13 +08:00
my_range = range
class CompilerTest(MPO):
parameters = "a b A B"
2014-05-31 00:20:13 +08:00
2014-06-17 04:56:08 +08:00
def print_done(self):
print("Done!")
2014-06-17 05:51:43 +08:00
def set_some_slowdev(self, n):
print("Slow device setting: {}".format(n))
2014-06-17 04:56:08 +08:00
2014-05-31 00:20:13 +08:00
@kernel
def run(self, n, t2):
for i in my_range(n):
2014-06-17 05:51:43 +08:00
self.set_some_slowdev(i)
delay(100*ms)
2014-05-31 00:20:13 +08:00
with parallel:
with sequential:
2014-06-23 00:52:37 +08:00
for j in my_range(3):
self.a.pulse((j+1)*100*MHz, 20*us)
self.b.pulse(100*MHz, t2)
2014-05-31 00:20:13 +08:00
with sequential:
self.A.pulse(100*MHz, 10*us)
self.B.pulse(100*MHz, t2)
2014-06-17 04:56:08 +08:00
self.print_done()
2014-05-31 00:20:13 +08:00
if __name__ == "__main__":
from artiq.devices import corecom_dummy, core, dds_core
2014-05-31 00:20:13 +08:00
coredev = core.Core(corecom_dummy.CoreCom())
2014-05-31 00:20:13 +08:00
exp = CompilerTest(
core=coredev,
a=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=0, rtio_channel=0),
b=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=1, rtio_channel=1),
A=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=2, rtio_channel=2),
B=dds_core.DDS(core=coredev, dds_sysclk=1*GHz, reg_channel=3, rtio_channel=3)
2014-05-31 00:20:13 +08:00
)
exp.run(3, 100*us)