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artiq/doc/manual/core_drivers_reference.rst

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doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
Core drivers reference
======================
doc: document core device driver. Closes #119
2015-10-06 18:12:57 +08:00
These drivers are for the core device and the peripherals closely integrated into it, which do not use the controller mechanism.
:mod:`artiq.coredevice.core` module
-----------------------------------
.. automodule:: artiq.coredevice.core
:members:
doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
coredevice: rename rtio to ttl, integrated in+out driver, loopback on the same pin in tests
2015-05-02 10:35:21 +08:00
:mod:`artiq.coredevice.ttl` module
sawg: documentation
2016-12-07 02:25:40 +08:00
----------------------------------
doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
coredevice: rename rtio to ttl, integrated in+out driver, loopback on the same pin in tests
2015-05-02 10:35:21 +08:00
.. automodule:: artiq.coredevice.ttl
doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
:members:
:mod:`artiq.coredevice.dds` module
----------------------------------
.. automodule:: artiq.coredevice.dds
:members:
Implement recording of DMA traces on the core device.
2017-02-26 10:50:20 +08:00
:mod:`artiq.coredevice.dma` module
----------------------------------
.. automodule:: artiq.coredevice.dma
:members:
coredevice.spi, doc/manual: add spi
2016-03-02 04:29:09 +08:00
:mod:`artiq.coredevice.spi` module
----------------------------------
.. automodule:: artiq.coredevice.spi
:members:
ad53xx->ad5360 and refactor
2016-03-04 07:00:25 +08:00
:mod:`artiq.coredevice.ad5360` module
-------------------------------------
.. automodule:: artiq.coredevice.ad5360
:members:
coredevice.spi, doc/manual: add spi
2016-03-02 04:29:09 +08:00
doc: I2C/QC2
2016-03-05 19:02:03 +08:00
:mod:`artiq.coredevice.i2c` module
----------------------------------
.. automodule:: artiq.coredevice.i2c
:members:
coredevice: put cache into separate file/device
2016-03-10 10:45:16 +08:00
:mod:`artiq.coredevice.cache` module
sawg: documentation
2016-12-07 02:25:40 +08:00
------------------------------------
coredevice: put cache into separate file/device
2016-03-10 10:45:16 +08:00
.. automodule:: artiq.coredevice.cache
:members:
manual: artiq.coredevice.runtime_exceptions -> artiq.coredevice.exceptions
2016-01-14 05:40:44 +08:00
:mod:`artiq.coredevice.exceptions` module
-----------------------------------------
doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
manual: artiq.coredevice.runtime_exceptions -> artiq.coredevice.exceptions
2016-01-14 05:40:44 +08:00
.. automodule:: artiq.coredevice.exceptions
doc/manual: split core/controller drivers
2014-10-27 16:41:48 +08:00
:members:
phaser: add jesd204b rtio dds gateware: add jesd204b awg gateware: copy phaser (df3825a) dsp/tools: update satadd mixin phaser: no DDS stubs dsp: accu fix phaser: cleanup/reduce sawg: kernel support and docs sawg: coredevice api fixes sawg: example ddb/experiment phaser: add conda package examples/phaser: typo sawg: adapt tests, fix accu stb sawg: tweak dds parameters sawg: move/adapt/extend tests sawg: test phy, refactor phaser: non-rtio spi phaser: target cli update phaser: ad9154-fmc-ebz pins phaser: reorganize fmc signal naming phaser: add test mode stubs phaser: txen is LVTTL phaser: clk spi xfer test phaser: spi for ad9154 and ad9516 phaser: spi tweaks ad9154: add register map from ad9144.xml ad9516: add register map from ad9517.xml and manual adaptation ad9154_reg: just generate getter/setter macros as well ad9154: reg WIP ad9154: check and fix registers kc705: single ended rtio_external_clk use single ended user_sma_clk_n instead of p/n to free up one clock sma kc705: mirror clk200 at user_sma_clock_p ad9516_regs.h: fix B_COUNTER_MSB phase: wire up clocking differently needs patched misoc kc705: feed rtio_external_clock directly kc705: remove rtio_external_clk for phaser phaser: spi tweaks ad9516: some startup ad9516_reg fixes phaser: setup ad9516 for supposed 500 MHz operation ad9516: use full duplex spi ad9154_reg: add CONFIG_REG_2 ad9154_reg: fixes phaser: write some ad9154 config ad9154_reg: fixes ad9154: more init, and human readable setup ad9154/ad9516: merge spi support ad9154: status readout Revert "kc705: remove rtio_external_clk for phaser" This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366. Revert "kc705: feed rtio_external_clock directly" This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5. Revert "phase: wire up clocking differently" This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc. Revert "kc705: mirror clk200 at user_sma_clock_p" This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba. Revert "kc705: single ended rtio_external_clk" This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf. ad9516: 2000 MHz clock phaser: test clock dist phaser: test freqs ad9154: iostandards phaser: drop clock monitor phaser: no separate i2c phaser: drive rtio from refclk, wire up sysref phaser: ttl channel for sync ad9154: 4x interp, status, tweaks phaser: sync/sysref 33V banks phaser: sync/sysref LVDS_25 inputs are VCCO tolerant phaser: user input-only ttls phaser: rtio fully from refclk ad9154: reg name usage fix ad9154: check register modifications Revert "ad9154: check register modifications" This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564. ad9154: fix status code ad9154: addrinc, recal serdes pll phaser: coredevice, example tweaks sawg: missing import sawg: type fixes ad9514: move setup functions ad9154: msb first also decreasing addr phaser: use sys4x for rtio internal ref phaser: move init code to main phaser: naming cleanup phaser: cleanup pins phaser: move spi to kernel cpu phaser: kernel support for ad9154 spi ad9154: add r/w methods ad9154: need return annotations ad9154: r/w methods are kernels ad9154_reg: portable helpers phaser: cleanup startup kernel ad9154: status test ad9154: prbs test ad9154: move setup, document phaser: more documentation
2016-07-22 21:56:09 +08:00
sawg: documentation
2016-12-07 02:25:40 +08:00
:mod:`artiq.coredevice.spline` module
-------------------------------------
.. automodule:: artiq.coredevice.spline
:members:
phaser: add jesd204b rtio dds gateware: add jesd204b awg gateware: copy phaser (df3825a) dsp/tools: update satadd mixin phaser: no DDS stubs dsp: accu fix phaser: cleanup/reduce sawg: kernel support and docs sawg: coredevice api fixes sawg: example ddb/experiment phaser: add conda package examples/phaser: typo sawg: adapt tests, fix accu stb sawg: tweak dds parameters sawg: move/adapt/extend tests sawg: test phy, refactor phaser: non-rtio spi phaser: target cli update phaser: ad9154-fmc-ebz pins phaser: reorganize fmc signal naming phaser: add test mode stubs phaser: txen is LVTTL phaser: clk spi xfer test phaser: spi for ad9154 and ad9516 phaser: spi tweaks ad9154: add register map from ad9144.xml ad9516: add register map from ad9517.xml and manual adaptation ad9154_reg: just generate getter/setter macros as well ad9154: reg WIP ad9154: check and fix registers kc705: single ended rtio_external_clk use single ended user_sma_clk_n instead of p/n to free up one clock sma kc705: mirror clk200 at user_sma_clock_p ad9516_regs.h: fix B_COUNTER_MSB phase: wire up clocking differently needs patched misoc kc705: feed rtio_external_clock directly kc705: remove rtio_external_clk for phaser phaser: spi tweaks ad9516: some startup ad9516_reg fixes phaser: setup ad9516 for supposed 500 MHz operation ad9516: use full duplex spi ad9154_reg: add CONFIG_REG_2 ad9154_reg: fixes phaser: write some ad9154 config ad9154_reg: fixes ad9154: more init, and human readable setup ad9154/ad9516: merge spi support ad9154: status readout Revert "kc705: remove rtio_external_clk for phaser" This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366. Revert "kc705: feed rtio_external_clock directly" This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5. Revert "phase: wire up clocking differently" This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc. Revert "kc705: mirror clk200 at user_sma_clock_p" This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba. Revert "kc705: single ended rtio_external_clk" This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf. ad9516: 2000 MHz clock phaser: test clock dist phaser: test freqs ad9154: iostandards phaser: drop clock monitor phaser: no separate i2c phaser: drive rtio from refclk, wire up sysref phaser: ttl channel for sync ad9154: 4x interp, status, tweaks phaser: sync/sysref 33V banks phaser: sync/sysref LVDS_25 inputs are VCCO tolerant phaser: user input-only ttls phaser: rtio fully from refclk ad9154: reg name usage fix ad9154: check register modifications Revert "ad9154: check register modifications" This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564. ad9154: fix status code ad9154: addrinc, recal serdes pll phaser: coredevice, example tweaks sawg: missing import sawg: type fixes ad9514: move setup functions ad9154: msb first also decreasing addr phaser: use sys4x for rtio internal ref phaser: move init code to main phaser: naming cleanup phaser: cleanup pins phaser: move spi to kernel cpu phaser: kernel support for ad9154 spi ad9154: add r/w methods ad9154: need return annotations ad9154: r/w methods are kernels ad9154_reg: portable helpers phaser: cleanup startup kernel ad9154: status test ad9154: prbs test ad9154: move setup, document phaser: more documentation
2016-07-22 21:56:09 +08:00
:mod:`artiq.coredevice.sawg` module
-----------------------------------
.. automodule:: artiq.coredevice.sawg
:members:
urukul: document ad9912, and cpld, fix api
2018-02-14 16:45:17 +08:00
:mod:`artiq.coredevice.urukul` module
-------------------------------------
.. automodule:: artiq.coredevice.urukul
:members:
:mod:`artiq.coredevice.ad9912` module
-------------------------------------
.. automodule:: artiq.coredevice.ad9912
:members:
:mod:`artiq.coredevice.ad9910` module
-------------------------------------
.. automodule:: artiq.coredevice.ad9910
:members: