forked from M-Labs/artiq
coredevice.spi, doc/manual: add spi
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@ -21,9 +21,25 @@ SPI_RT2WB_READ = 1 << 2
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class SPIMaster:
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"""Core device Serial Peripheral Interface (SPI) bus master.
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Owns one SPI bus.
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**Transfer Sequence**:
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* If desired, write the ``config`` register (:meth:`set_config`)
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to configure and activate the core.
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* If desired, write the ``xfer`` register (:meth:`set_xfer`)
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to set ``cs_n``, ``write_length``, and ``read_length``.
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* :meth:`write` to the ``data`` register (also for transfers with
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zero bits to be written). Writing starts the transfer.
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* If desired, :meth:`read_sync` (or :meth:`read_async` followed by a
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:meth:`input_async` later) the ``data`` register corresponding to
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the last completed transfer.
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* If desired, :meth:`set_xfer` for the next transfer.
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* If desired, :meth:`write` ``data`` queuing the next
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(possibly chained) transfer.
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:param ref_period: clock period of the SPI core.
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:param channel: channel number of the SPI bus to control.
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:param channel: RTIO channel number of the SPI bus to control.
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"""
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def __init__(self, dmgr, ref_period, channel):
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self.core = dmgr.get("core")
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@ -43,12 +59,69 @@ class SPIMaster:
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@kernel
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def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
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"""Set the configuration register.
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* If ``config.cs_polarity`` == 0 (```cs`` active low, the default),
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"``cs_n`` all deasserted" means "all ``cs_n`` bits high".
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* ``cs_n`` is not mandatory in the pads supplied to the gateware core.
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Framing and chip selection can also be handled independently
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through other means, e.g. ``TTLOut``.
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* If there is a ``miso`` wire in the pads supplied in the gateware,
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input and output may be two signals ("4-wire SPI"),
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otherwise ``mosi`` must be used for both output and input
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("3-wire SPI") and ``config.half_duplex`` must to be set
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when reading data is desired or when the slave drives the
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``mosi`` signal at any point.
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* The first bit output on ``mosi`` is always the MSB/LSB (depending
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on ``config.lsb_first``) of the ``data`` register, independent of
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``xfer.write_length``. The last bit input from ``miso`` always ends
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up in the LSB/MSB (respectively) of the ``data`` register,
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independent of ``xfer.read_length``.
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* Writes to the ``config`` register take effect immediately.
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**Configuration flags**:
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* :const:`SPI_OFFLINE`: all pins high-z (reset=1)
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* :const:`SPI_ACTIVE`: transfer in progress (read-only)
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* :const:`SPI_PENDING`: transfer pending in intermediate buffer
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(read-only)
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* :const:`SPI_CS_POLARITY`: active level of ``cs_n`` (reset=0)
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* :const:`SPI_CLK_POLARITY`: idle level of ``clk`` (reset=0)
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* :const:`SPI_CLK_PHASE`: first edge after ``cs`` assertion to sample
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data on (reset=0). In Motorola/Freescale SPI language
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(:const:`SPI_CLK_POLARITY`, :const:`SPI_CLK_PHASE`) == (CPOL, CPHA):
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- (0, 0): idle low, output on falling, input on rising
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- (0, 1): idle low, output on rising, input on falling
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- (1, 0): idle high, output on rising, input on falling
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- (1, 1): idle high, output on falling, input on rising
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* :const:`SPI_LSB_FIRST`: LSB is the first bit on the wire (reset=0)
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* :const:`SPI_HALF_DUPLEX`: 3-wire SPI, in/out on ``mosi`` (reset=0)
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This method advances the timeline by the duration of the
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RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
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:param flags: A bit map of `SPI_*` flags.
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:param write_freq: Desired SPI clock frequency during write bits.
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:param read_freq: Desired SPI clock frequency during read bits.
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"""
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write_div = round(1/(write_freq*self.ref_period))
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read_div = round(1/(read_freq*self.ref_period))
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self.set_config_mu(flags, write_div, read_div)
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@kernel
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def set_config_mu(self, flags=0, write_div=6, read_div=6):
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"""Set the ``config`` register (in SPI bus machine units).
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.. seealso:: :meth:`set_config`
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:param write_div: Counter load value to divide the RTIO
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clock by to generate the SPI write clk. (minimum=2, reset=2)
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``f_rtio_clk/f_spi_write == write_div``. If ``write_div`` is odd,
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the setup phase of the SPI clock is biased to longer lengths
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by one RTIO clock cycle.
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:param read_div: Ditto for the read clock.
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"""
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rtio_output(now_mu(), self.channel, SPI_CONFIG_ADDR, flags |
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((write_div - 2) << 16) | ((read_div - 2) << 24))
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self.write_period_mu = int(write_div*self.ref_period_mu)
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@ -57,6 +130,43 @@ class SPIMaster:
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@kernel
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def set_xfer(self, chip_select=0, write_length=0, read_length=0):
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"""Set the ``xfer`` register.
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* Every transfer consists of a write of ``write_length`` bits
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immediately followed by a read of ``read_length`` bits.
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* ``cs_n`` is asserted at the beginning and deasserted at the end
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of the transfer if there is no other transfer pending.
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* ``cs_n`` handling is agnostic to whether it is one-hot or decoded
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somewhere downstream. If it is decoded, "``cs_n`` all deasserted"
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should be handled accordingly (no slave selected).
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If it is one-hot, asserting multiple slaves should only be attempted
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if ``miso`` is either not connected between slaves, or open
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collector, or correctly multiplexed externally.
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* For 4-wire SPI only the sum of ``read_length`` and ``write_length``
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matters. The behavior is the same (except for clock speeds) no matter
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how the total transfer length is divided between the two. For
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3-wire SPI, the direction of ``mosi`` is switched from output to
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input after ``write_length`` bits.
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* Data output on ``mosi`` in 4-wire SPI during the read cycles is what
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is found in the data register at the time.
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Data in the ``data`` register outside the least/most (depending
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on ``config.lsb_first``) significant ``read_length`` bits is what is
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seen on ``miso`` (or ``mosi`` if ``config.half_duplex``)
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during the write cycles.
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* Writes to ``xfer`` are synchronized to the start of the next
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(possibly chained) transfer.
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This method advances the timeline by the duration of the
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RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
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:param chip_select: Bit mask of chip selects to assert. Or number of
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the chip select to assert if ``cs`` is decoded downstream.
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(reset=0)
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:param write_length: Number of bits to write during the next transfer.
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(reset=0)
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:param read_length: Number of bits to read during the next transfer.
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(reset=0)
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"""
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rtio_output(now_mu(), self.channel, SPI_XFER_ADDR,
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chip_select | (write_length << 16) | (read_length << 24))
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self.xfer_period_mu = int(write_length*self.write_period_mu +
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@ -65,24 +175,64 @@ class SPIMaster:
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@kernel
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def write(self, data):
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"""Write data to data register.
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* The ``data`` register and the shift register are 32 bits wide.
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If there are no writes to the register, ``miso`` data reappears on
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``mosi`` after 32 cycles.
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* A wishbone data register write is acknowledged when the
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transfer has been written to the intermediate buffer.
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It will be started when there are no other transactions being
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executed, either beginning a new SPI transfer of chained
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to an in-flight transfer.
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* Writes take three ``ref_period`` cycles unless another
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chained transfer is pending and the transfer being
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executed is not complete.
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* The SPI ``data`` register is double-buffered: Once a transfer has
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started, new write data can be written, queuing a new transfer.
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Transfers submitted this way are chained and executed without
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deasserting ``cs`` in between. Once a transfer completes,
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the previous transfer's read data is available in the
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``data`` register.
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This method advances the timeline by the duration of the
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RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
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"""
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rtio_output(now_mu(), self.channel, SPI_DATA_ADDR, data)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def read_async(self):
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# every read_async() must be matched by an input_async()
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"""Trigger an asynchronous read from the data register.
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Reads always finish in two cycles.
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Every data register read triggered by a :meth:`read_async`
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must be matched by a :meth:`input_async` to retrieve the data.
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This method advances the timeline by the duration of the
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RTIO-to-Wishbone bus transaction (three RTIO clock cycles).
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"""
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rtio_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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delay_mu(3*self.ref_period_mu)
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@kernel
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def input_async(self):
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# matches the preeeding read_async()
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"""Retrieves data written asynchronously.
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:meth:`input_async` must match a preeeding :meth:`read_async`.
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"""
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return rtio_input_data(self.channel)
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@kernel
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def read_sync(self):
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rtio_output(now_mu(), self.channel, SPI_DATA_ADDR | SPI_RT2WB_READ, 0)
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return rtio_input_data(self.channel)
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"""Read the ``data`` register synchronously.
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This is a shortcut for :meth:`read_async` followed by
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:meth:`input_async`.
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"""
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self.read_async()
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return self.input_async()
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@kernel
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def _get_xfer_sync(self):
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@ -19,11 +19,18 @@ These drivers are for the core device and the peripherals closely integrated int
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----------------------------------
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.. autoclass:: artiq.coredevice.dds._DDSGeneric
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:members:
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:members:
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.. automodule:: artiq.coredevice.dds
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:members:
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:mod:`artiq.coredevice.spi` module
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----------------------------------
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.. automodule:: artiq.coredevice.spi
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:members:
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:mod:`artiq.coredevice.exceptions` module
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-----------------------------------------
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