forked from M-Labs/artiq
1
0
Fork 0

coredevice: put cache into separate file/device

This commit is contained in:
Sebastien Bourdeauducq 2016-03-10 10:45:16 +08:00
parent 7f501820de
commit 1739e0f2f8
5 changed files with 61 additions and 39 deletions

45
artiq/coredevice/cache.py Normal file
View File

@ -0,0 +1,45 @@
from artiq.language.core import *
from artiq.language.types import *
@syscall
def cache_get(key: TStr) -> TList(TInt32):
raise NotImplementedError("syscall not simulated")
@syscall
def cache_put(key: TStr, value: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")
class CoreCache:
"""Core device cache access"""
def __init__(self, dmgr, core_device="core"):
self.core = dmgr.get(core_device)
@kernel
def get(self, key):
"""Extract a value from the core device cache.
After a value is extracted, it cannot be replaced with another value using
:meth:`put` until all kernel functions finish executing; attempting
to replace it will result in a :class:`artiq.coredevice.exceptions.CacheError`.
If the cache does not contain any value associated with ``key``, an empty list
is returned.
The value is not copied, so mutating it will change what's stored in the cache.
:param str key: cache key
:return: a list of 32-bit integers
"""
return cache_get(key)
@kernel
def put(self, key, value):
"""Put a value into the core device cache. The value will persist until reboot.
To remove a value from the cache, call :meth:`put` with an empty list.
:param str key: cache key
:param list value: a list of 32-bit integers
"""
cache_put(key, value)

View File

@ -41,14 +41,6 @@ class CompileError(Exception):
def rtio_get_counter() -> TInt64:
raise NotImplementedError("syscall not simulated")
@syscall
def cache_get(key: TStr) -> TList(TInt32):
raise NotImplementedError("syscall not simulated")
@syscall
def cache_put(key: TStr, value: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")
class Core:
"""Core device driver.
@ -127,31 +119,3 @@ class Core:
min_now = rtio_get_counter() + 125000
if now_mu() < min_now:
at_mu(min_now)
@kernel
def get_cache(self, key):
"""Extract a value from the core device cache.
After a value is extracted, it cannot be replaced with another value using
:meth:`put_cache` until all kernel functions finish executing; attempting
to replace it will result in a :class:`artiq.coredevice.exceptions.CacheError`.
If the cache does not contain any value associated with ``key``, an empty list
is returned.
The value is not copied, so mutating it will change what's stored in the cache.
:param str key: cache key
:return: a list of 32-bit integers
"""
return cache_get(key)
@kernel
def put_cache(self, key, value):
"""Put a value into the core device cache. The value will persist until reboot.
To remove a value from the cache, call :meth:`put_cache` with an empty list.
:param str key: cache key
:param list value: a list of 32-bit integers
"""
cache_put(key, value)

View File

@ -5,21 +5,22 @@ from artiq.test.hardware_testbench import ExperimentCase
class _Cache(EnvExperiment):
def build(self):
self.setattr_device("core")
self.print = lambda x: print(x)
self.setattr_device("core_cache")
@kernel
def get(self, key):
return self.core.get_cache(key)
return self.core_cache.get(key)
@kernel
def put(self, key, value):
self.core.put_cache(key, value)
self.core_cache.put(key, value)
@kernel
def get_put(self, key, value):
self.get(key)
self.put(key, value)
class CacheTest(ExperimentCase):
def test_get_empty(self):
exp = self.create(_Cache)

View File

@ -42,6 +42,12 @@ These drivers are for the core device and the peripherals closely integrated int
.. automodule:: artiq.coredevice.i2c
:members:
:mod:`artiq.coredevice.cache` module
-----------------------------------------
.. automodule:: artiq.coredevice.cache
:members:
:mod:`artiq.coredevice.exceptions` module
-----------------------------------------

View File

@ -1,5 +1,6 @@
# This is an example device database that needs to be adapted to your setup.
# The RTIO channel numbers here are for NIST CLOCK on KC705.
# The list of devices here is not exhaustive.
{
"comm": {
@ -14,6 +15,11 @@
"class": "Core",
"arguments": {"ref_period": 1e-9}
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dds": {
"type": "local",
"module": "artiq.coredevice.dds",