forked from M-Labs/zynq-rs
319 lines
8.9 KiB
Rust
319 lines
8.9 KiB
Rust
//! Quad-SPI Flash Controller
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use core::marker::PhantomData;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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use super::clocks::CpuClocks;
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pub mod regs;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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const SINGLE_CAPACITY: u32 = 16 * 1024 * 1024;
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pub struct LinearAddressing;
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pub struct Manual;
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/// Flash Interface Driver
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///
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/// For 2x Spansion S25FL128SAGMFIR01
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pub struct Flash<MODE> {
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regs: &'static mut regs::RegisterBlock,
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_mode: PhantomData<MODE>,
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}
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impl<MODE> Flash<MODE> {
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fn transition<TO>(self) -> Flash<TO> {
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Flash {
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regs: self.regs,
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_mode: PhantomData,
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}
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}
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}
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impl Flash<()> {
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pub fn new(clock: u32) -> Self {
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Self::enable_clocks(clock);
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Self::setup_signals();
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Self::reset();
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs, _mode: PhantomData };
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flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
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flash
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}
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fn enable_clocks(clock: u32) {
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let io_pll = CpuClocks::get().io;
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let divisor = ((clock - 1 + io_pll) / clock)
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.max(1).min(63) as u8;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_clk_ctrl.write(
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slcr::LqspiClkCtrl::zeroed()
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.src_sel(slcr::PllSource::IoPll)
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.divisor(divisor)
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.clkact(true)
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);
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});
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}
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fn setup_signals() {
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slcr::RegisterBlock::unlocked(|slcr| {
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// 1. Configure MIO pin 1 for chip select 0 output.
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slcr.mio_pin_01.write(
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slcr::MioPin01::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Configure MIO pins 2 through 5 for I/O.
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slcr.mio_pin_02.write(
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slcr::MioPin02::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_03.write(
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slcr::MioPin03::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_04.write(
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slcr::MioPin04::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_05.write(
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slcr::MioPin05::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// 3. Configure MIO pin 6 for serial clock 0 output.
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slcr.mio_pin_06.write(
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slcr::MioPin06::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// Option: Add Second Device Chip Select
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// 4. Configure MIO pin 0 for chip select 1 output.
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slcr.mio_pin_00.write(
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slcr::MioPin00::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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);
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// Option: Add Second Serial Clock
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// 5. Configure MIO pin 9 for serial clock 1 output.
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slcr.mio_pin_09.write(
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slcr::MioPin09::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// Option: Add 4-bit Data
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// 6. Configure MIO pins 10 through 13 for I/O.
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slcr.mio_pin_10.write(
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slcr::MioPin10::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_11.write(
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slcr::MioPin11::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_12.write(
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slcr::MioPin12::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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slcr.mio_pin_13.write(
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slcr::MioPin13::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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// Option: Add Feedback Output Clock
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// 7. Configure MIO pin 8 for feedback clock.
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slcr.mio_pin_08.write(
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slcr::MioPin08::zeroed()
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.l0_sel(true)
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.io_type(slcr::IoBufferType::Lvcmos18)
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);
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});
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}
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fn reset() {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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.ref_rst(true)
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.cpu1x_rst(true)
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);
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slcr.lqspi_rst_ctrl.write(
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slcr::LqspiRstCtrl::zeroed()
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);
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});
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}
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fn configure(&mut self, divider: u32) {
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self.disable_interrupts();
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self.clear_rx_fifo();
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// for a baud_rate_div=1 LPBK_DLY_ADJ would be required
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let mut baud_rate_div = 2u32;
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while baud_rate_div < 7 && 2u32.pow(1 + baud_rate_div) < divider {
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baud_rate_div += 1;
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}
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self.regs.config.write(regs::Config::zeroed()
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.leg_flsh(true)
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// 32 bits TX FIFO width
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.fifo_width(0b11)
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);
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// Initialize RX/TX pipes thresholds
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unsafe {
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self.regs.rx_thres.write(32);
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self.regs.tx_thres.write(1);
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}
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}
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fn disable_interrupts(&mut self) {
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self.regs.intr_dis.write(
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regs::IntrDis::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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}
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}
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pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
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// Set manual start enable to auto mode.
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// Assert the chip select.
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self.regs.config.modify(|_, w| w
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.man_start_en(false)
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.pcs(false)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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// Quad I/O Fast Read
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.inst_code(0xEB)
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.mode_bits(0xFF)
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.dummy_byte(0x2)
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.mode_en(true)
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// 2 devices
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.two_mem(true)
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// Linear Addressing Mode
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.lq_mode(true)
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);
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self.regs.enable.modify(|_, w| w.spi_en(true));
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self.transition()
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}
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pub fn manual_mode(self, chip_index: usize) -> Flash<Manual> {
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self.regs.config.modify(|_, w| w
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.man_start_en(true)
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.manual_cs(true)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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.mode_bits(0xFF)
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.dummy_byte(0x2)
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.mode_en(true)
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// 2 devices
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.two_mem(true)
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.u_page(chip_index != 0)
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);
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self.regs.config.modify(|_, w| w
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.pcs(false)
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);
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self.regs.enable.modify(|_, w| w.spi_en(true));
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self.transition()
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}
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}
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impl Flash<LinearAddressing> {
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/// Stop linear addressing mode
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pub fn stop(self) -> Flash<()> {
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self.regs.enable.modify(|_, w| w.spi_en(false));
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// De-assert chip select.
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self.regs.config.modify(|_, w| w.pcs(true));
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self.transition()
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}
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pub fn ptr<T>(&mut self) -> *mut T {
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0xFC00_0000 as *mut _
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}
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pub fn size(&self) -> usize {
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2 * (SINGLE_CAPACITY as usize)
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}
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}
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impl Flash<Manual> {
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pub fn stop(self) -> Flash<()> {
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self.regs.enable.modify(|_, w| w.spi_en(false));
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// De-assert chip select.
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self.regs.config.modify(|_, w| w.pcs(true));
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self.transition()
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}
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pub fn read(&mut self, offset: u32, dest: &mut [u8]) {
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self.regs.config.modify(|_, w| w.man_start_com(true));
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// Quad I/O Read
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let instr = 0xEB;
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unsafe {
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self.regs.txd0.write(
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instr |
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(offset << 8)
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);
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}
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while self.regs.intr_status.read().tx_fifo_not_full() {
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unsafe {
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self.regs.txd0.write(0);
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}
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let rx = self.regs.rx_data.read();
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}
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for d in dest {
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while !self.regs.intr_status.read().rx_fifo_not_empty() {}
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// TODO: drops data?
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let rx = self.regs.rx_data.read();
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*d = rx as u8;
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// Output dummy byte to generate clock for further RX
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unsafe {
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self.regs.txd1.write(0);
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}
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}
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}
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fn wait_tx_not_full(&self) {
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while self.regs.intr_status.read().tx_fifo_full() {}
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}
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}
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