6 Commits (74c43b34773ab78c98831d234567ba3a6d31e699)

Author	SHA1	Message	Date
Astro	74c43b3477	zynq::eth::tx: clear entry.word1 for each packet	2019-11-04 02:31:40 +01:00
Astro	99a00e019b	zynq::eth: implement phy::extended_status, set clock for link speed	2019-11-04 02:30:00 +01:00
Astro	961e2e1dd0	zynq::{ddr, eth}: fix clock divisor calculation ... off-by-one, didn't change behavior.	2019-11-03 02:23:16 +01:00
Astro	6bee1f44f4	zynq: replace unnecessary slcr::unlocked with new	2019-10-31 20:48:07 +01:00
Astro	5c62716a99	zynq::eth: switch rx and tx descriptor words to vcell ... vcell can be initialized cleanly.	2019-10-31 03:15:13 +01:00
Astro	c046bbf8a2	move slcr, clocks, uart, eth into src/zynq/	2019-10-21 22:19:03 +02:00