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zynq::ddr: parameters

master
Astro 2019-10-27 20:38:06 +01:00
parent 27114aec62
commit 85bd506132
3 changed files with 33 additions and 30 deletions
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2
src/main.rs
View File

@ -87,7 +87,7 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
fn main() { fn main() {
println!("Main."); println!("Main.");
zynq::clocks::CpuClocks::enable_ddr(1_066_000_000); zynq::clocks::CpuClocks::enable_ddr(1_066_666_666);
let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read(); let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read();
println!("PLLs: {}", pll_status); println!("PLLs: {}", pll_status);
let clocks = zynq::clocks::CpuClocks::get(); let clocks = zynq::clocks::CpuClocks::get();

47
src/zynq/clocks.rs
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@ -94,34 +94,35 @@ impl CpuClocks {
/// 25.10.4 PLLs /// 25.10.4 PLLs
pub fn enable_ddr(target_clock: u32) { pub fn enable_ddr(target_clock: u32) {
let fdiv = (target_clock / PS_CLK).min(66) as u16; let fdiv = (target_clock / PS_CLK).min(66) as u16;
let regs = slcr::RegisterBlock::new();
regs.ddr_pll_ctrl.modify(|_, w| w
.pll_pwrdwn(false)
.pll_bypass_force(true)
.pll_fdiv(fdiv)
);
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter() let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max) .filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.nth(0) .nth(0)
.expect("PLL_FDIV_LOCK_PARAM") .expect("PLL_FDIV_LOCK_PARAM")
.1.clone(); .1.clone();
regs.ddr_pll_cfg.write( slcr::RegisterBlock::unlocked(|regs| {
slcr::PllCfg::zeroed() regs.ddr_pll_ctrl.modify(|_, w| w
.pll_res(pll_res) .pll_pwrdwn(false)
.pll_cp(pll_cp) .pll_bypass_force(true)
.lock_cnt(lock_cnt) .pll_fdiv(fdiv)
); );
regs.ddr_pll_ctrl.modify(|_, w| w regs.ddr_pll_cfg.write(
.pll_reset(true) slcr::PllCfg::zeroed()
); .pll_res(pll_res)
regs.ddr_pll_ctrl.modify(|_, w| w .pll_cp(pll_cp)
.pll_reset(false) .lock_cnt(lock_cnt)
); );
while ! regs.pll_status.read().ddr_pll_lock() {} regs.ddr_pll_ctrl.modify(|_, w| w
regs.ddr_pll_ctrl.modify(|_, w| w .pll_reset(true)
.pll_bypass_force(false) );
.pll_bypass_qual(false) regs.ddr_pll_ctrl.modify(|_, w| w
); .pll_reset(false)
);
while ! regs.pll_status.read().ddr_pll_lock() {}
regs.ddr_pll_ctrl.modify(|_, w| w
.pll_bypass_force(false)
.pll_bypass_qual(false)
);
});
} }
} }

14
src/zynq/ddr/mod.rs
View File

@ -36,7 +36,7 @@ impl DdrRam {
/// Zynq-7000 AP SoC Technical Reference Manual: /// Zynq-7000 AP SoC Technical Reference Manual:
/// 10.6.1 DDR Clock Initialization /// 10.6.1 DDR Clock Initialization
fn clock_setup(clocks: &CpuClocks) { fn clock_setup(clocks: &CpuClocks) {
CpuClocks::enable_ddr(1_066_000_000); CpuClocks::enable_ddr(1_066_666_666);
let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
@ -181,14 +181,16 @@ impl DdrRam {
// TODO: move into trait // TODO: move into trait
pub fn ptr(&mut self) -> *mut u8 { pub fn ptr(&mut self) -> *mut u8 {
// 0x0010_0000 as *mut _ 0x0010_0000 as *mut _
0x0020_0000 as *mut _
} }
pub fn size(&self) -> usize { pub fn size(&self) -> usize {
// #[cfg(feature = "target_zc706")] #[cfg(feature = "target_zc706")]
// 1024 * 1024 * 1024 let megabytes = 1024;
4 * 1024 * 1024 #[cfg(feature = "target_cora_z7_10")]
let megabytes = 512;
megabytes * 1024 * 1024
} }
pub fn memtest(&mut self) { pub fn memtest(&mut self) {