5568: init

There aren't any electrical specs, as suggested by the lack of electronic components.
There is a colored version of the connection diagram, but I think the B&W one actually looks better.

2245.tex

@@ -621,13 +621,13 @@ The following examples will assume the SPI communication has the following prope
     \item Full duplex
 \end{itemize}
 The base line configuration for an \texttt{SPIMaster} instance can be defined as such:
-\inputcolorboxminted[0]{firstline=105,lastline=110}{examples/ttl.py}
+\inputcolorboxminted[0]{firstline=2,lastline=8}{examples/spi.py}
 The \texttt{SPI\char`_END} \& \texttt{SPI\char`_INPUT} flags will be modified during runtime in the following example.
 
 \subsubsection{SPI frequency}
 Frequency of the SPI clock must be the result of RTIO clock frequency divided by an integer factor from [2, 257].
 In the folowing examples, the SPI frequency will be set to 1 MHz by dividing the RTIO frequency (125 MHz) by 125.
-\inputcolorboxminted[0]{firstline=112,lastline=112}{examples/ttl.py}
+\inputcolorboxminted[0]{firstline=10,lastline=10}{examples/spi.py}
 
 \subsubsection{SPI write}
 Typically, an SPI write operation involves sending an instruction and data to the SPI slaves.
@@ -654,7 +654,7 @@ The timing diagram of such write operation is shown in the following.
 
 \newpage
 Suppose the instruction is \texttt{0x13}, while the data is \texttt{0xDEADBEEF}. In addition, both slave 1 \& 2 are selected. This SPI transcation can be performed by the following code.
-\inputcolorboxminted{firstline=119,lastline=128}{examples/ttl.py}
+\inputcolorboxminted{firstline=18,lastline=27}{examples/spi.py}
 
 \subsubsection{SPI read}
 A 32-bits read is represented by the following timing diagram.
@@ -679,7 +679,7 @@ A 32-bits read is represented by the following timing diagram.
 \end{center}
 
 Suppose the instruction is \texttt{0x81}, where only slave 0 is selected. This SPI transcation can be performed by the following code.
-\inputcolorboxminted{firstline=136,lastline=150}{examples/ttl.py}
+\inputcolorboxminted{firstline=35,lastline=49}{examples/spi.py}
 
 \newpage
 \section{Ordering Information}

5568.tex

@@ -0,0 +1,135 @@
+\documentclass[10pt]{datasheet}
+\usepackage{palatino}
+\usepackage{textgreek}
+\usepackage{minted}
+\usepackage{tcolorbox}
+\usepackage{etoolbox}
+
+\usepackage[justification=centering]{caption}
+
+\usepackage[utf8]{inputenc}
+\usepackage[english]{babel}
+\usepackage[english]{isodate}
+
+\usepackage{graphicx}
+\usepackage{subfig}
+
+\usepackage{tikz}
+\usepackage{pgfplots}
+\usepackage{circuitikz}
+\usepackage{pifont}
+\usetikzlibrary{calc}
+\usetikzlibrary{fit,backgrounds} 
+
+\title{5568 HD68-IDC}
+\author{M-Labs Limited}
+\date{January 2022}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+\begin{itemize}
+    \item{32 channels.}
+    \item{Internal IDC connector.}
+    \item{External HD68 connectors.}
+\end{itemize}
+
+\section{Applications}
+
+\begin{itemize}
+    \item{Branch out analog signal from: \begin{itemize}
+        \item{5432 DAC Zotino}
+        \item{5632 DAC Fastino}
+    \end{itemize}}
+    \item{BNC or SMA adapter when used with: \begin{itemize}
+        \item{5518 BNC-IDC}
+        \item{5528 SMA-IDC}
+    \end{itemize}}
+\end{itemize}
+
+\section{General Description}
+The 5568 HD68-IDC card is a 4hp EEM module part of the ARTIQ Sinara family.
+It is an adapter that converts IDC connection from/to HD68 connection.
+It connects to an external HD68 cable to 5518 BNC-IDC or 5528 SMA-IDC cards.
+
+Each card support 32 channels, with 1 HD68 connector and 4 IDC connectors.
+Each IDC connector supports 8 channels, while all 32 channels are accessible using an external HD68 cable.
+
+% Switch to next column
+\vfill\break
+
+\newcommand*{\MyLabel}[3][2cm]{\parbox{#1}{\centering #2 \\ #3}}
+\newcommand*{\MymyLabel}[3][4cm]{\parbox{#1}{\centering #2 \\ #3}}
+\newcommand{\repeatfootnote}[1]{\textsuperscript{\ref{#1}}}
+\newcommand{\inputcolorboxminted}[2]{%
+    \begin{tcolorbox}[colback=white]
+    \inputminted[#1, gobble=4]{python}{#2}
+    \end{tcolorbox}
+}
+
+\begin{figure}[h]
+    \centering
+    \scalebox{1}{
+    \begin{circuitikz}[european, scale=0.95, every label/.append style={align=center}]
+
+        % HD68 Connector
+        \draw (0, 0) node[muxdemux, muxdemux def={Lh=6.5, Rh=8, w=2, NL=0, NB=0, NR=0}, circuitikz/bipoles/twoport/width=3.2, scale=0.7] (hd68) {HD68};
+
+        % IDC Connectors to IDC cards
+        \draw (3.0, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 16-23}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem2) {};
+        \draw (1.8, 1.8) node[twoportshape, t={\MyLabel{IDC}{CH 24-31}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem3) {};
+        \draw (3.0, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 8-15}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem1) {};
+        \draw (1.8, -1.8) node[twoportshape, t={\MyLabel{IDC}{CH 0-7}}, circuitikz/bipoles/twoport/width=1.8, scale=0.7, rotate=-90] (eem0) {};
+
+        % Connect Op-amp to EEM OUT and HD68
+        \draw [-latexslim] (3.0, 0) -- (hd68.east);
+        \draw [-latexslim] (3.0, 0) -- (eem2.east);
+        \draw [-latexslim] (1.8, 0) -- (eem3.east);
+        \draw [-latexslim] (3.0, 0) -- (eem1.west);
+        \draw [-latexslim] (1.8, 0) -- (eem0.west);
+
+    \end{circuitikz}
+    }
+
+    \caption{Simplified Block Diagram}
+\end{figure}
+
+\begin{figure}[h]
+    \centering
+    \includegraphics[height=2.1in]{HD68_IDC_FP.pdf}
+    \includegraphics[height=2.1in]{photo5568.jpg}
+    \caption{HD68-IDC Card photo}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\section{Cable Connection Diagram}
+The 5568 HD68-IDC card can convert signal from HD68 format to IDC format.
+In the Sinara family, analog output of 5432 DAC Zotino \& 5632 DAC Fastino cards are exported using HD68 connectors.
+To break out the analog signal in a different crate, connect 5568 HD68-IDC with the DAC card using an external SCSI cable.
+Then, plug in IDC cables to the appropriate IDC connectors to break out the signal to 5518 BNC-IDC or 5528 SMA-IDC cards.
+The cable connections for 5568 HD68-IDC can be seen in the diagram below.
+\begin{figure}[h]
+    \centering
+    \includegraphics[height=5in]{hd68_idc_connection.pdf}
+    \caption{HD68-IDC connection diagram}
+\end{figure}
+
+\section{Ordering Information}
+To order, please visit \url{https://m-labs.hk} and select the 5568 HD68-IDC in the ARTIQ Sinara crate configuration tool.
+The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
+
+\section*{}
+\vspace*{\fill}
+
+\begin{footnotesize}
+Information furnished by M-Labs Limited is provided in good faith in the hope that it will be useful. However, no responsibility is assumed by M-Labs Limited for its use. Specifications may be subject to change without notice.
+\end{footnotesize}
+
+\end{document}

examples/spi.py

@@ -0,0 +1,49 @@
+from artiq.experiment import *
+from artiq.coredevice import spi2 as spi
+
+
+SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
+              0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
+              0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
+              0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
+
+CLK_DIV = 125
+
+
+class SPIWrite(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.spi = self.get_device("dio_spi0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
+        self.spi.write(0x13 << 24)      # Shift the bits to the MSBs.
+                                        # Since SPI_LSB_FIRST is NOT set,
+                                        # SPI Machine will shift out bits from
+                                        # the MSB of the `data` register.`
+        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
+        self.spi.write(0xDEADBEEF)
+
+
+class SPIRead(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.spi = self.get_device("dio_spi0")
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
+        self.spi.write(0x81 << 24)      # Shift the bits to the MSBs.
+                                        # Since SPI_LSB_FIRST is NOT set,
+                                        # SPI Machine will shift out bits from
+                                        # the MSB of the `data` register.`
+        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
+                                32, CLK_DIV, 0b001)
+        self.spi.write(0)               # write() performs the SPI transfer.
+                                        # As suggested by the timing diagram,
+                                        # the exact value of this argument
+                                        # does not matter.
+        print(self.spi.read())

examples/ttl.py

@@ -101,50 +101,3 @@ class ClockGen(EnvExperiment):
     def run(self):
         self.core.reset()
         self.ttl0.set(62.5*MHz)
-
-from artiq.coredevice import spi2 as spi
-
-SPI_CONFIG = (0 * spi.SPI_OFFLINE | 0 * spi.SPI_END |
-              0 * spi.SPI_INPUT | 0 * spi.SPI_CS_POLARITY |
-              0 * spi.SPI_CLK_POLARITY | 0 * spi.SPI_CLK_PHASE |
-              0 * spi.SPI_LSB_FIRST | 0 * spi.SPI_HALF_DUPLEX)
-
-CLK_DIV = 125
-
-class SPIWrite(EnvExperiment):
-    def build(self):
-        self.setattr_device("core")
-        self.spi = self.get_device("dio_spi0")
-
-    @kernel
-    def run(self):
-        self.core.reset()
-        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b110)
-        self.spi.write(0x13 << 24)      # Shift the bits to the MSBs.
-                                        # Since SPI_LSB_FIRST is NOT set,
-                                        # SPI Machine will shift out bits from
-                                        # the MSB of the `data` register.`
-        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END, 32, CLK_DIV, 0b110)
-        self.spi.write(0xDEADBEEF)
-
-
-class SPIRead(EnvExperiment):
-    def build(self):
-        self.setattr_device("core")
-        self.spi = self.get_device("dio_spi0")
-
-    @kernel
-    def run(self):
-        self.core.reset()
-        self.spi.set_config_mu(SPI_CONFIG, 8, CLK_DIV, 0b001)
-        self.spi.write(0x81 << 24)      # Shift the bits to the MSBs.
-                                        # Since SPI_LSB_FIRST is NOT set,
-                                        # SPI Machine will shift out bits from
-                                        # the MSB of the `data` register.`
-        self.spi.set_config_mu(SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
-                                32, CLK_DIV, 0b001)
-        self.spi.write(0)               # write() performs the SPI transfer.
-                                        # As suggested by the timing diagram,
-                                        # the exact value of this argument
-                                        # does not matter.
-        print(self.spi.read())