occheung
087663d7e0
2238: add photo
2022-01-03 17:21:34 +08:00
occheung
05b7f12c2b
2238: init
2022-01-03 17:21:05 +08:00
occheung
09b07575e0
2245: clarify single EEM
2022-01-03 17:13:49 +08:00
occheung
0ca9115088
2245: remove ESD spec
...
This spec refers to the LVDS repeaters only, other ICs may have lower ESD specs.
2022-01-03 09:59:12 +08:00
occheung
dfb1d8028c
2245: fix I/O direction line on CH8-15
2021-12-31 17:40:04 +08:00
occheung
325585db97
2245: fix switch symbol position
2021-12-31 17:36:19 +08:00
occheung
12c0114189
2245: init
2021-12-31 17:34:16 +08:00
occheung
b583eef5f6
5432: add plots
2021-12-30 15:00:43 +08:00
occheung
a84ba87184
5432: add additional plots
...
https://github.com/sinara-hw/Zotino/issues/21
Step response & FEXT.
2021-12-30 14:33:54 +08:00
occheung
a231d13d7a
5432: update applications
2021-12-30 14:33:04 +08:00
occheung
f86b663e1d
4410-4412: add figures
2021-12-24 16:49:45 +08:00
occheung
337ecbd6ae
4410-4412: add more specs
2021-12-24 16:36:58 +08:00
occheung
e6674c76e4
4410-4412: add harmonic content with generic output frequencies
...
https://github.com/sinara-hw/Urukul/issues/29
Other harmonic content info may become obsolete.
2021-12-24 16:34:30 +08:00
occheung
cd8c211462
4410-4412: update applications
2021-12-24 16:33:20 +08:00
occheung
3ff0209452
2118: add photo
2021-12-23 12:56:49 +08:00
occheung
a32c43c0b8
2128 -> 2118/2128
2021-12-23 12:56:11 +08:00
occheung
534ef5c6ed
4410-4412: fix layout
2021-12-22 17:19:27 +08:00
occheung
bc4e11cdf6
4410-4412: separate RAM SYNC example
2021-12-22 17:17:03 +08:00
occheung
9251da4ce0
4410-4412/RAM: add amplitude ramp example
2021-12-22 17:16:21 +08:00
occheung
4b3f0c5612
4410-4412/RAM: replace screenshot with plot
2021-12-22 17:14:57 +08:00
occheung
1ce032605a
4410-4412/RAM: lower background frequency to 5MHz
...
It is to make the plot easier for our eyes.
2021-12-22 17:12:48 +08:00
occheung
d26fe0f5d5
4410-4412: configure_ram_mode add slack
...
When the RAM data is larger, extra slack is needed to avoid underflow.
2021-12-22 17:10:57 +08:00
occheung
9b40af6c6a
4410-4412: add graphs for phase noise/harmonic contents
2021-12-22 12:17:23 +08:00
occheung
82521ff909
4410-4412: enlarge photo
...
And prevent the photo from jumping to the next page.
2021-12-22 09:53:06 +08:00
occheung
3c633dfa27
5432: clarify op-amp label
...
In case the x32 notation (somehow) looks like 32 op-amps in series.
2021-12-09 12:42:17 +08:00
occheung
ce04f3f749
5432: fix order info
2021-12-09 12:35:39 +08:00
occheung
6beaac676d
5432: init
2021-12-09 12:33:42 +08:00
occheung
b538ef7858
4410-4412: add unit when calling set_att()
2021-12-08 12:19:31 +08:00
occheung
2127697fe6
4410-4412: update set() parameters
...
Note that the `frequency` param is mandatory in AD9912.set(), while optional in AD9910.set()
2021-12-08 12:17:27 +08:00
occheung
b9c7dcec67
4410: add amp modulation waveform
2021-12-07 16:38:56 +08:00
occheung
aa96ed4ab3
4410: fix whitespace in ram example
2021-12-07 16:35:03 +08:00
occheung
60861ccf1f
4410: mention default profile for single-tone
2021-12-07 16:29:35 +08:00
occheung
8f1a437378
4410: add ram modulation with synchronization example
2021-12-07 16:26:25 +08:00
occheung
011d63f3eb
4410: modify ram example
...
* Use `prepare()` to init the arrays, would be great if the value can be prepared there. However, the type check was not happy about it.
* Separate RAM configuration into a separate function
* Separate DDS init, digital attenuation & switch config in an init function
* Use `dds.set()`. It is supposed to look simple.
All these are to avoid repeating the long code in the coming RAM+SYNC example.
2021-12-07 16:21:56 +08:00
occheung
0dbf7a70c4
4410: add phase param to single-tone sync e.g.
...
+- 0.25 turns w.r.t the other channel, excluding I/O update mismatch
2021-12-07 16:20:18 +08:00
occheung
7265d05bae
4410-4412: remove leftover comment
2021-12-07 16:19:05 +08:00
occheung
b657e0fea5
4410-4412: clarify nominal power
...
The same figure can be found in sinara issue 354 / urukul issue 3, and it was meant to be an empirical limit for low frequency RF outputs.
2021-12-06 13:17:19 +08:00
occheung
ca896ed094
4410-4412: fix phase noise layout, add harmonics
2021-12-06 13:06:24 +08:00
occheung
e109ec2b6f
4410-4412: fix performance data condition
...
The condition should now align with wiki and sinara issue 354 / urukul issue 3.
2021-12-06 13:05:46 +08:00
occheung
41c6e37c74
4410-4412: fix caption
2021-12-06 12:39:35 +08:00
occheung
894823d2d4
4410-4412: remove phase param from single-tone e.g.
2021-12-06 11:53:45 +08:00
occheung
74bc8ef797
4410-4412: add waveform for ram mod e.g.
2021-12-06 11:52:31 +08:00
occheung
11b1aee030
4410-4412: specify digital for attenuator specs
2021-12-06 10:46:39 +08:00
occheung
3b4b44c833
4410-4412: remove air flow spec
2021-12-06 10:43:49 +08:00
occheung
c5c8701341
4410-4412: fix photo
2021-12-02 13:31:04 +08:00
occheung
69da8ea9b4
4410 -> 4410-4412, 4410/4412
2021-12-02 13:29:35 +08:00
occheung
5837353cab
4410: fix table/text sequence
2021-12-02 10:13:14 +08:00
occheung
0b28c4fbb2
4410: fix condition case
2021-12-02 09:56:47 +08:00
occheung
cf9d395947
4410: add recommended env
2021-12-01 16:13:44 +08:00
occheung
5c18e9267d
4410 diagram: sync only available to AD9910
2021-12-01 13:03:42 +08:00
occheung