2 Commits

Author	SHA1	Message	Date
Jack-Zheng	6535ff5423	LVDS&IO: add fpga flash config; all: fix connection bugs; PCB: initialize component positions and layout	2021-06-22 16:34:02 +08:00
Jack-Zheng	982fefd6b5	all: update gitigore to fix symbol and footpin bugs; replace messy libs into one	2021-06-21 16:05:17 +08:00