Syrostan/TestAutomation.sch-bak

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EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 6
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 8300 3850 2050 2150
U 60C2FE2A
F0 "Power" 50
F1 "Power.sch" 50
$EndSheet
$Sheet
S 1000 1000 1950 2550
U 60C2FDBB
F0 "MCU" 50
F1 "MCU.sch" 50
F2 "CPU_DAC0" I L 1000 1150 50
F3 "CPU_DAC1" I L 1000 1250 50
F4 "CPU_ADC1" I L 1000 1500 50
F5 "CPU_ADC2" I L 1000 1600 50
F6 "CPU_ADC3" I L 1000 1700 50
F7 "CPU_ADC4" I L 1000 1800 50
F8 "CPU_ADC0" I L 1000 1400 50
F9 "CPU_ADC5" I L 1000 1900 50
F10 "CPU_ADC6" I L 1000 2000 50
F11 "CPU_ADC7" I L 1000 2100 50
$EndSheet
$Sheet
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U 60E4702B
F0 "Ethernet" 50
F1 "Ethernet.sch" 50
F2 "POE_VC+" I L 2250 5200 50
F3 "POE_VC-" I L 2250 5100 50
F4 "ENC_SPI_SCK" I L 2250 4900 50
F5 "ENC_SPI_MOSI" I L 2250 4800 50
F6 "ENC_SPI_MISO" I L 2250 4700 50
F7 "ENC_INT" I L 2250 4400 50
F8 "ENC_SPI_CS" I L 2250 4600 50
$EndSheet
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$Sheet
S 8250 950 600 1200
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U 60FB17F2
F0 "High_Speed_ADC" 50
F1 "High_Speed_ADC.sch" 50
F2 "ADC_IN" I L 8250 1050 50
F3 "ADC_CLK" I L 8250 1200 50
F4 "ADC_DATA1" I L 8250 1350 50
F5 "ADC_DATA2" I L 8250 1450 50
F6 "ADC_DATA3" I L 8250 1550 50
F7 "ADC_DATA4" I L 8250 1650 50
F8 "ADC_DATA5" I L 8250 1750 50
F9 "ADC_DATA6" I L 8250 1850 50
F10 "ADC_DATA7" I L 8250 1950 50
F11 "ADC_DATA8" I L 8250 2050 50
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$EndSheet
$Sheet
S 4450 800 1500 5450
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U 60C0E996
F0 "FPGA" 50
F1 "FPGA.sch" 50
F2 "FPGA_VPP_FAST" I L 4450 4500 50
F3 "FPGA_EEM0_0_P" I R 5950 850 50
F4 "FPGA_EEM0_0_N" I R 5950 950 50
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F15 "FPGA_EEM0_2_P" I R 5950 1250 50
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F33 "FPGA_EEM1_1_P" I R 5950 2850 50
F34 "FPGA_EEM1_1_N" I R 5950 2950 50
F35 "FPGA_EEM2_0_P" I R 5950 4450 50
F36 "FPGA_EEM2_0_N" I R 5950 4550 50
F37 "FPGA_EEM2_7_P" I R 5950 5850 50
F38 "FPGA_EEM2_7_N" I R 5950 5950 50
F39 "FPGA_EEM2_6_P" I R 5950 5650 50
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F47 "FPGA_EEM2_2_P" I R 5950 4850 50
F48 "FPGA_EEM2_2_N" I R 5950 4950 50
F49 "FPGA_EEM2_1_P" I R 5950 4650 50
F50 "FPGA_EEM2_1_N" I R 5950 4750 50
F51 "FPGA_IIC0_SDA" I R 5950 2550 50
F52 "FPGA_IIC0_SCL" I R 5950 2450 50
F53 "FPGA_IIC1_SDA" I R 5950 4350 50
F54 "FPGA_IIC1_SCL" I R 5950 4250 50
F55 "FPGA_IIC2_SDA" I R 5950 6150 50
F56 "FPGA_IIC2_SCL" I R 5950 6050 50
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F58 "FPGA_FSMC_A1" I L 4450 950 50
F59 "FPGA_FSMC_A2" I L 4450 1050 50
F60 "FPGA_FSMC_A3" I L 4450 1150 50
F61 "FPGA_FSMC_A4" I L 4450 1250 50
F62 "FPGA_FSMC_A5" I L 4450 1350 50
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F64 "FPGA_FSMC_A7" I L 4450 1550 50
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F79 "FPGA_FSMC_D14" I L 4450 3050 50
F80 "FPGA_FSMC_D15" I L 4450 3150 50
F81 "FPGA_CSBSEL0" I L 4450 3500 50
F82 "FPGA_CSBSEL1" I L 4450 3600 50
F83 "FPGA_SPI_SDO" I L 4450 3700 50
F84 "FPGA_SPI_SDI" I L 4450 3800 50
F85 "FPGA_SPI_SS" I L 4450 3900 50
F86 "FPGA_SPI_SCK" I L 4450 4000 50
F87 "FPGA_CDONE" I L 4450 4100 50
F88 "FPGA_CRESET" I L 4450 4200 50
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$EndSheet
$EndSCHEMATC