2021-06-10 15:16:21 +08:00
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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2021-06-15 16:49:17 +08:00
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Sheet 1 6
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2021-06-10 15:16:21 +08:00
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 5550 1100 2050 2550
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U 60C0E996
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F0 "FPGA" 50
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F1 "FPGA.sch" 50
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F2 "FPGA_VCC" I R 7600 1300 50
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F3 "FPGA_GND" I R 7600 1600 50
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$EndSheet
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$Sheet
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S 2150 5000 2050 2150
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U 60C2FE2A
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F0 "Power" 50
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F1 "Power.sch" 50
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$EndSheet
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$Sheet
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S 5600 5000 2000 1450
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U 60FB17F2
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F0 "Analog_LVDS" 50
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F1 "Analog_LVDS.sch" 50
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2021-06-16 11:36:49 +08:00
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F2 "ADC_DATA_BUS" I L 5600 5150 50
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2021-06-10 15:16:21 +08:00
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$EndSheet
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2021-06-15 16:49:17 +08:00
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$Sheet
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S 2150 1100 1950 2550
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U 60C2FDBB
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F0 "MCU" 50
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F1 "MCU.sch" 50
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F2 "CPU_DAC0" I L 2150 1250 50
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F3 "CPU_DAC1" I L 2150 1350 50
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F4 "CPU_ADC1" I L 2150 1600 50
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F5 "CPU_ADC2" I L 2150 1700 50
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F6 "CPU_ADC3" I L 2150 1800 50
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F7 "CPU_ADC4" I L 2150 1900 50
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F8 "CPU_ADC0" I L 2150 1500 50
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F9 "CPU_ADC5" I L 2150 2000 50
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F10 "CPU_ADC6" I L 2150 2100 50
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F11 "CPU_ADC7" I L 2150 2200 50
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$EndSheet
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$Sheet
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S 9150 2050 1200 1400
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U 60E4702B
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F0 "Ethernet" 50
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F1 "Ethernet.sch" 50
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2021-06-16 11:36:49 +08:00
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F2 "POE_VC+" I L 9150 3300 50
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F3 "POE_VC-" I L 9150 3150 50
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F4 "ENC_SPI_SCK" I L 9150 2750 50
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F5 "ENC_SPI_MOSI" I L 9150 2650 50
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F6 "ENC_SPI_MISO" I L 9150 2550 50
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F7 "ENC_INT" I L 9150 2350 50
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F8 "ENC_SPI_CS" I L 9150 2450 50
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2021-06-15 16:49:17 +08:00
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$EndSheet
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2021-06-16 11:36:49 +08:00
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Wire Bus Line
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5600 5150 5450 5150
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Entry Wire Line
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5350 4450 5450 4550
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Entry Wire Line
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5350 4550 5450 4650
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Entry Wire Line
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5350 4650 5450 4750
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Entry Wire Line
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5350 4750 5450 4850
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Entry Wire Line
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5350 4850 5450 4950
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Entry Wire Line
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5350 4950 5450 5050
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Entry Wire Line
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5350 5050 5450 5150
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Entry Wire Line
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5350 4350 5450 4450
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Wire Wire Line
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5350 4350 5100 4350
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Wire Wire Line
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5100 4350 5100 4300
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Wire Wire Line
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5350 4450 5100 4450
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Wire Bus Line
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5450 4400 5450 5150
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2021-06-10 15:16:21 +08:00
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$EndSCHEMATC
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