2021-06-10 15:16:21 +08:00
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EESchema Schematic File Version 4
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EELAYER 30 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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2021-06-15 16:49:17 +08:00
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Sheet 1 6
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2021-06-10 15:16:21 +08:00
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Sheet
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S 2150 5000 2050 2150
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U 60C2FE2A
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F0 "Power" 50
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F1 "Power.sch" 50
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$EndSheet
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$Sheet
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2021-06-15 16:49:17 +08:00
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S 2150 1100 1950 2550
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U 60C2FDBB
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F0 "MCU" 50
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F1 "MCU.sch" 50
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F2 "CPU_DAC0" I L 2150 1250 50
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F3 "CPU_DAC1" I L 2150 1350 50
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F4 "CPU_ADC1" I L 2150 1600 50
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F5 "CPU_ADC2" I L 2150 1700 50
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F6 "CPU_ADC3" I L 2150 1800 50
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F7 "CPU_ADC4" I L 2150 1900 50
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F8 "CPU_ADC0" I L 2150 1500 50
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F9 "CPU_ADC5" I L 2150 2000 50
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F10 "CPU_ADC6" I L 2150 2100 50
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F11 "CPU_ADC7" I L 2150 2200 50
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$EndSheet
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$Sheet
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S 9150 2050 1200 1400
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U 60E4702B
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F0 "Ethernet" 50
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F1 "Ethernet.sch" 50
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2021-06-16 11:36:49 +08:00
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F2 "POE_VC+" I L 9150 3300 50
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F3 "POE_VC-" I L 9150 3150 50
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F4 "ENC_SPI_SCK" I L 9150 2750 50
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F5 "ENC_SPI_MOSI" I L 9150 2650 50
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F6 "ENC_SPI_MISO" I L 9150 2550 50
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F7 "ENC_INT" I L 9150 2350 50
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F8 "ENC_SPI_CS" I L 9150 2450 50
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2021-06-15 16:49:17 +08:00
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$EndSheet
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2021-06-16 15:23:18 +08:00
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$Sheet
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2021-06-16 17:13:34 +08:00
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S 9200 4250 600 1200
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2021-06-16 15:23:18 +08:00
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U 60FB17F2
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F0 "High_Speed_ADC" 50
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F1 "High_Speed_ADC.sch" 50
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2021-06-16 17:13:34 +08:00
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F2 "ADC_IN" I L 9200 4350 50
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F3 "ADC_CLK" I L 9200 4500 50
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F4 "ADC_DATA1" I L 9200 4650 50
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F5 "ADC_DATA2" I L 9200 4750 50
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F6 "ADC_DATA3" I L 9200 4850 50
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F7 "ADC_DATA4" I L 9200 4950 50
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F8 "ADC_DATA5" I L 9200 5050 50
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F9 "ADC_DATA6" I L 9200 5150 50
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F10 "ADC_DATA7" I L 9200 5250 50
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F11 "ADC_DATA8" I L 9200 5350 50
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$EndSheet
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$Sheet
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S 5550 1100 1500 5450
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U 60C0E996
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F0 "FPGA" 50
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F1 "FPGA.sch" 50
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F2 "FPGA_VPP_FAST" I L 5550 4800 50
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F3 "FPGA_EEM0_0_P" I R 7050 1150 50
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F4 "FPGA_EEM0_0_N" I R 7050 1250 50
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F5 "FPGA_EEM0_7_P" I R 7050 2550 50
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F6 "FPGA_EEM0_7_N" I R 7050 2650 50
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F7 "FPGA_EEM0_6_P" I R 7050 2350 50
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F8 "FPGA_EEM0_6_N" I R 7050 2450 50
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F9 "FPGA_EEM0_5_P" I R 7050 2150 50
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F10 "FPGA_EEM0_5_N" I R 7050 2250 50
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F11 "FPGA_EEM0_4_P" I R 7050 1950 50
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F12 "FPGA_EEM0_4_N" I R 7050 2050 50
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F13 "FPGA_EEM0_3_P" I R 7050 1750 50
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F14 "FPGA_EEM0_3_N" I R 7050 1850 50
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F15 "FPGA_EEM0_2_P" I R 7050 1550 50
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F16 "FPGA_EEM0_2_N" I R 7050 1650 50
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F17 "FPGA_EEM0_1_P" I R 7050 1350 50
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F18 "FPGA_EEM0_1_N" I R 7050 1450 50
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F19 "FPGA_EEM1_0_P" I R 7050 2950 50
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F20 "FPGA_EEM1_0_N" I R 7050 3050 50
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F21 "FPGA_EEM1_7_P" I R 7050 4350 50
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F22 "FPGA_EEM1_7_N" I R 7050 4450 50
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F23 "FPGA_EEM1_6_P" I R 7050 4150 50
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F24 "FPGA_EEM1_6_N" I R 7050 4250 50
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F25 "FPGA_EEM1_5_P" I R 7050 3950 50
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F26 "FPGA_EEM1_5_N" I R 7050 4050 50
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F27 "FPGA_EEM1_4_P" I R 7050 3750 50
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F28 "FPGA_EEM1_4_N" I R 7050 3850 50
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F29 "FPGA_EEM1_3_P" I R 7050 3550 50
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F30 "FPGA_EEM1_3_N" I R 7050 3650 50
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F31 "FPGA_EEM1_2_P" I R 7050 3350 50
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F32 "FPGA_EEM1_2_N" I R 7050 3450 50
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F33 "FPGA_EEM1_1_P" I R 7050 3150 50
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F34 "FPGA_EEM1_1_N" I R 7050 3250 50
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F35 "FPGA_EEM2_0_P" I R 7050 4750 50
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F36 "FPGA_EEM2_0_N" I R 7050 4850 50
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F37 "FPGA_EEM2_7_P" I R 7050 6150 50
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F38 "FPGA_EEM2_7_N" I R 7050 6250 50
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F39 "FPGA_EEM2_6_P" I R 7050 5950 50
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F40 "FPGA_EEM2_6_N" I R 7050 6050 50
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F41 "FPGA_EEM2_5_P" I R 7050 5750 50
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F42 "FPGA_EEM2_5_N" I R 7050 5850 50
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F43 "FPGA_EEM2_4_P" I R 7050 5550 50
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F44 "FPGA_EEM2_4_N" I R 7050 5650 50
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F45 "FPGA_EEM2_3_P" I R 7050 5350 50
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F46 "FPGA_EEM2_3_N" I R 7050 5450 50
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F47 "FPGA_EEM2_2_P" I R 7050 5150 50
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F48 "FPGA_EEM2_2_N" I R 7050 5250 50
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F49 "FPGA_EEM2_1_P" I R 7050 4950 50
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F50 "FPGA_EEM2_1_N" I R 7050 5050 50
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F51 "FPGA_IIC0_SDA" I R 7050 2850 50
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F52 "FPGA_IIC0_SCL" I R 7050 2750 50
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F53 "FPGA_IIC1_SDA" I R 7050 4650 50
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F54 "FPGA_IIC1_SCL" I R 7050 4550 50
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F55 "FPGA_IIC2_SDA" I R 7050 6450 50
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F56 "FPGA_IIC2_SCL" I R 7050 6350 50
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F57 "FPGA_FSMC_A0" I L 5550 1150 50
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F58 "FPGA_FSMC_A1" I L 5550 1250 50
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F59 "FPGA_FSMC_A2" I L 5550 1350 50
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F60 "FPGA_FSMC_A3" I L 5550 1450 50
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F61 "FPGA_FSMC_A4" I L 5550 1550 50
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F62 "FPGA_FSMC_A5" I L 5550 1650 50
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F63 "FPGA_FSMC_A6" I L 5550 1750 50
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F64 "FPGA_FSMC_A7" I L 5550 1850 50
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F65 "FPGA_FSMC_D0" I L 5550 1950 50
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F66 "FPGA_FSMC_D1" I L 5550 2050 50
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F67 "FPGA_FSMC_D2" I L 5550 2150 50
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F68 "FPGA_FSMC_D3" I L 5550 2250 50
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F69 "FPGA_FSMC_D4" I L 5550 2350 50
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F70 "FPGA_FSMC_D5" I L 5550 2450 50
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F71 "FPGA_FSMC_D6" I L 5550 2550 50
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F72 "FPGA_FSMC_D7" I L 5550 2650 50
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F73 "FPGA_FSMC_D8" I L 5550 2750 50
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F74 "FPGA_FSMC_D9" I L 5550 2850 50
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F75 "FPGA_FSMC_D10" I L 5550 2950 50
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F76 "FPGA_FSMC_D11" I L 5550 3050 50
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F77 "FPGA_FSMC_D12" I L 5550 3150 50
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F78 "FPGA_FSMC_D13" I L 5550 3250 50
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F79 "FPGA_FSMC_D14" I L 5550 3350 50
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F80 "FPGA_FSMC_D15" I L 5550 3450 50
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F81 "FPGA_CSBSEL0" I L 5550 3800 50
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F82 "FPGA_CSBSEL1" I L 5550 3900 50
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F83 "FPGA_SPI_SDO" I L 5550 4000 50
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F84 "FPGA_SPI_SDI" I L 5550 4100 50
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F85 "FPGA_SPI_SS" I L 5550 4200 50
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F86 "FPGA_SPI_SCK" I L 5550 4300 50
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F87 "FPGA_CDONE" I L 5550 4400 50
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F88 "FPGA_CRESET" I L 5550 4500 50
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2021-06-16 15:23:18 +08:00
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$EndSheet
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2021-06-10 15:16:21 +08:00
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$EndSCHEMATC
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