102 lines
2.3 KiB
Coq
102 lines
2.3 KiB
Coq
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module top (
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HW_CLK,
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LED,
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KEY,
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DIO_OUT,
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DIO_IO_SEL,
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DIO_CH_SEL,
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ADC_CLK,
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ADC_DAT,
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FSMC_CLK,
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FSMC_DA,
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FSMC_NL,
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FSMC_NWAIT,
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FSMC_NOE,
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FSMC_NWE,
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FSMC_NBL,
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FSMC_NE1
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);
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/* I/O */
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input HW_CLK;
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input KEY;
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output LED;
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input FSMC_NL;
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input FSMC_NOE;
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input FSMC_NWE;
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input FSMC_NE1;
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inout [15:0]FSMC_DA;
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input [1:0]FSMC_NBL;
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input FSMC_CLK;
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input FSMC_NWAIT;
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output ADC_CLK;
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input [7:0]ADC_DAT;
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output DIO_OUT;
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output DIO_IO_SEL;
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output [2:0]DIO_CH_SEL;
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reg [15:0] FSMC_add = 16'b0;
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/* Counter register */
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reg [31:0] counter = 32'b0;
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/* LED drivers */
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// assign LED = counter[24];
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// assign LED = ~KEY;
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/* always */
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always @ (posedge HW_CLK) begin
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counter <= counter + 1;
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end
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/* high-speed ADC */
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assign ADC_CLK = HW_CLK;
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reg [7:0] adc_buf = 8'b0;
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always @ (posedge ADC_CLK) begin
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adc_buf = ADC_DAT;
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adc_buf[7] = ~adc_buf[7];
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// FSMC_DA = adc_buf;
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end
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/* FSMC */
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reg [15:0] out_data = 16'h0000;
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wire FSMC_ADV = ~FSMC_NE1 & ~FSMC_NL;
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always @ (posedge FSMC_ADV)
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begin
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// LED = ~LED;
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FSMC_add[15:0] = FSMC_DA[15:0];
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end
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// assign LED = FSMC_add[0];
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wire FSMC_RE = ~FSMC_NOE & ~FSMC_NE1 & FSMC_NL;
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always @ (posedge FSMC_RE) begin //read from FPGA
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case (FSMC_add)
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0: out_data = 16'd0;
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1: out_data = 16'd1;
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2: out_data = 16'd2;
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63: out_data = 16'd123;
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default: out_data = 16'd0;
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endcase
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// out_data = FSMC_add;
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end
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wire FSMC_WE = ~FSMC_NWE & ~FSMC_NE1 & FSMC_NL;
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always @ (posedge FSMC_WE) begin //write to FPGA
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//4 bits for LVDS; 3 bits for channel select; 1 bit for IO direction control
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// DIO_IO_SEL <= FSMC_DA[0];
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// DIO_CH_SEL <= FSMC_DA[3:1];
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// if (DIO_CH_SEL == 3'b111)
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// LED = ~LED;
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end
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assign FSMC_DA = FSMC_RE ? out_data : 16'hzzzz;
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/* multiplexer control */
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// assign DIO_IO_SEL = FSMC_CLK;
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// assign DIO_CH_SEL[1:0] = FSMC_NBL[1:0];
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// assign DIO_CH_SEL[2] = FSMC_NWAIT;
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endmodule
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