module top (
            HW_CLK,
            LED,
            KEY,
            DIO_OUT,
            DIO_IO_SEL, 
            DIO_CH_SEL,
            ADC_CLK,
            ADC_DAT,
            FSMC_CLK,
            FSMC_DA,
            FSMC_NL,
            FSMC_NWAIT,
            FSMC_NOE,
            FSMC_NWE,
            FSMC_NBL,
            FSMC_NE1
        );

    /* I/O */
    input HW_CLK;
    input KEY;
    output LED;

    input FSMC_NL;
    input FSMC_NOE;
    input FSMC_NWE;
    input FSMC_NE1;
    inout [15:0]FSMC_DA;
    input [1:0]FSMC_NBL;
    input FSMC_CLK;
    input FSMC_NWAIT;

    output ADC_CLK;
    input [7:0]ADC_DAT;

    output DIO_OUT;
    output DIO_IO_SEL;
    output [2:0]DIO_CH_SEL;

    reg [15:0] FSMC_add = 16'b0;
    
    /* Counter register */
    reg [31:0] counter = 32'b0;
    /* LED drivers */
    // assign LED = counter[24];
    // assign LED = ~KEY;

    /* always */
    always @ (posedge HW_CLK) begin
        counter <= counter + 1;
    end

/* high-speed ADC */
    assign ADC_CLK = HW_CLK;
    reg [7:0] adc_buf = 8'b0;
    always @ (posedge ADC_CLK) begin
        adc_buf = ADC_DAT;
        adc_buf[7] = ~adc_buf[7];
        // FSMC_DA = adc_buf;
    end

/* FSMC */
    reg [15:0] out_data = 16'h0000;

    wire FSMC_ADV = ~FSMC_NE1 & ~FSMC_NL;
    always @ (posedge FSMC_ADV)
    begin
        // LED = ~LED;
        FSMC_add[15:0] = FSMC_DA[15:0];
    end

    // assign LED = FSMC_add[0];

    wire FSMC_RE = ~FSMC_NOE & ~FSMC_NE1 & FSMC_NL;
    always @ (posedge FSMC_RE) begin   //read from FPGA
        case (FSMC_add)
            0: out_data = 16'd0;
            1: out_data = 16'd1;
            2: out_data = 16'd2;
            63: out_data = 16'd123;
            default: out_data = 16'd0;
        endcase
        // out_data = FSMC_add;
    end

    wire FSMC_WE = ~FSMC_NWE & ~FSMC_NE1 & FSMC_NL;
    always @ (posedge FSMC_WE) begin   //write to FPGA
        //4 bits for LVDS; 3 bits for channel select; 1 bit for IO direction control
        // DIO_IO_SEL <= FSMC_DA[0];
        // DIO_CH_SEL <= FSMC_DA[3:1];
        // if (DIO_CH_SEL == 3'b111)
        //     LED = ~LED;
    end

    assign FSMC_DA = FSMC_RE ? out_data : 16'hzzzz;
/* multiplexer control */
    // assign DIO_IO_SEL = FSMC_CLK;
    // assign DIO_CH_SEL[1:0] = FSMC_NBL[1:0];
    // assign DIO_CH_SEL[2] = FSMC_NWAIT;
    
endmodule