change switch chips to MOS; finish PCB routing

Syrostan-Ext-DIO-cache.lib

@@ -358,6 +358,34 @@ X ~ 2 0 -150 110 U 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
+# Device_Q_NMOS_GSD
+#
+DEF Device_Q_NMOS_GSD Q 0 0 Y N 1 F N
+F0 "Q" 200 50 50 H V L CNN
+F1 "Device_Q_NMOS_GSD" 200 -50 50 H V L CNN
+F2 "" 200 100 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+C 65 0 110 0 1 10 N
+C 100 -70 10 0 1 0 F
+C 100 70 10 0 1 0 F
+P 2 0 1 0 10 0 -100 0 N
+P 2 0 1 10 10 75 10 -75 N
+P 2 0 1 10 30 -50 30 -90 N
+P 2 0 1 10 30 20 30 -20 N
+P 2 0 1 10 30 90 30 50 N
+P 2 0 1 0 100 100 100 70 N
+P 3 0 1 0 100 -100 100 0 30 0 N
+P 4 0 1 0 30 -70 130 -70 130 70 30 70 N
+P 4 0 1 0 40 0 80 15 80 -15 40 0 F
+P 4 0 1 0 110 20 115 15 145 15 150 10 N
+P 4 0 1 0 130 15 115 -10 145 -10 130 15 N
+X G 1 -200 0 100 R 50 50 1 1 I
+X S 2 100 -200 100 U 50 50 1 1 P
+X D 3 100 200 100 D 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
 # Device_R
 #
 DEF Device_R R 0 0 N Y 1 F N
@@ -421,26 +449,6 @@ X IN 6 400 -150 100 L 50 50 1 1 I
 ENDDRAW
 ENDDEF
 #
-# Syrostan-Ext-DIO_TS5A3359
-#
-DEF Syrostan-Ext-DIO_TS5A3359 U 0 40 Y Y 1 F N
-F0 "U" -150 50 50 H V C CNN
-F1 "Syrostan-Ext-DIO_TS5A3359" 0 -50 50 H V C CNN
-F2 "Package_SO:VSSOP-8_2.4x2.1mm_P0.5mm" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-S -200 -100 300 -500 0 1 0 N
-X NO0 1 -300 -150 100 R 50 50 1 1 B
-X NO1 2 -300 -250 100 R 50 50 1 1 B
-X NO2 3 -300 -350 100 R 50 50 1 1 B
-X GND 4 -300 -450 100 R 50 50 1 1 I
-X IN2 5 400 -450 100 L 50 50 1 1 I
-X IN1 6 400 -350 100 L 50 50 1 1 I
-X COM 7 400 -250 100 L 50 50 1 1 B
-X VCC 8 400 -150 100 L 50 50 1 1 I
-ENDDRAW
-ENDDEF
-#
 # power_+12V
 #
 DEF power_+12V #PWR 0 0 Y Y 1 F P
@@ -526,17 +534,4 @@ X GND2 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# power_GND3
-#
-DEF power_GND3 #PWR 0 0 Y Y 1 F P
-F0 "#PWR" 0 -250 50 H I C CNN
-F1 "power_GND3" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H I C CNN
-DRAW
-P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
-X GND3 1 0 0 0 D 50 50 1 1 W N
-ENDDRAW
-ENDDEF
-#
 #End Library

Syrostan-Ext-DIO.pro

@@ -1,4 +1,4 @@
-update=Fri Aug 20 16:51:08 2021
+update=Tue Aug 24 16:31:47 2021
 version=1
 last_client=kicad
 [general]
@@ -37,8 +37,8 @@ ViaDiameter1=0.8
 ViaDrill1=0.4
 ViaDiameter2=0.5
 ViaDrill2=0.3
-dPairWidth1=0.2
+dPairWidth1=0.254
-dPairGap1=0.25
+dPairGap1=0.127
 dPairViaGap1=0.25
 SilkLineWidth=0.12
 SilkTextSizeV=1
@@ -233,12 +233,12 @@ Enabled=0
 [pcbnew/Netclasses]
 [pcbnew/Netclasses/Default]
 Name=Default
-Clearance=0.2
+Clearance=0.127
 TrackWidth=0.254
 ViaDiameter=0.8
 ViaDrill=0.4
 uViaDiameter=0.3
 uViaDrill=0.1
-dPairWidth=0.2
+dPairWidth=0.254
-dPairGap=0.25
+dPairGap=0.127
 dPairViaGap=0.25