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examples: updated

This commit is contained in:
occheung 2021-01-21 13:03:33 +08:00
parent 056f812e60
commit eeeb162cc5
3 changed files with 61 additions and 17 deletions
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33
examples/delay.rs Normal file
View File

@ -0,0 +1,33 @@
use embedded_hal::blocking::delay::{DelayMs, DelayUs};
pub struct AsmDelay {
frequency_us: u32,
frequency_ms: u32,
}
impl AsmDelay {
pub fn new(freq: u32) -> AsmDelay {
AsmDelay {
frequency_us: (freq / 1_000_000),
frequency_ms: (freq / 1_000),
}
}
}
impl<U> DelayUs<U> for AsmDelay
where
U: Into<u32>,
{
fn delay_us(&mut self, us: U) {
cortex_m::asm::delay(self.frequency_us * us.into())
}
}
impl<U> DelayMs<U> for AsmDelay
where
U: Into<u32>,
{
fn delay_ms(&mut self, ms: U) {
cortex_m::asm::delay(self.frequency_ms * ms.into())
}
}

24
examples/tcp_stm32f407.rs
View File

@ -28,6 +28,9 @@ use smoltcp::socket::{SocketSet, TcpSocket, TcpSocketBuffer};
use core::str; use core::str;
use core::fmt::Write; use core::fmt::Write;
mod delay;
use delay::AsmDelay;
/// Timer /// Timer
use core::cell::RefCell; use core::cell::RefCell;
use cortex_m::interrupt::Mutex; use cortex_m::interrupt::Mutex;
@ -80,7 +83,9 @@ use stm32f4xx_hal::{
}; };
type BoosterSpiEth = enc424j600::SpiEth< type BoosterSpiEth = enc424j600::SpiEth<
Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>, Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
PA4<Output<PushPull>>>; PA4<Output<PushPull>>,
AsmDelay
>;
pub struct NetStorage { pub struct NetStorage {
ip_addrs: [IpCidr; 1], ip_addrs: [IpCidr; 1],
@ -122,7 +127,8 @@ const APP: () = {
.pclk1(42.mhz()) .pclk1(42.mhz())
.require_pll48clk() .require_pll48clk()
.freeze(); .freeze();
let mut delay = Delay::new(c.core.SYST, clocks); let asm_delay = AsmDelay::new(clocks.sysclk().0);
let mut hal_delay = Delay::new(c.core.SYST, clocks);
// Init ITM // Init ITM
let mut itm = c.core.ITM; let mut itm = c.core.ITM;
@ -142,7 +148,7 @@ const APP: () = {
// Map SPISEL: see Table 1, NIC100 Manual // Map SPISEL: see Table 1, NIC100 Manual
let mut spisel = gpioa.pa1.into_push_pull_output(); let mut spisel = gpioa.pa1.into_push_pull_output();
spisel.set_high().unwrap(); spisel.set_high().unwrap();
delay.delay_ms(1_u32); hal_delay.delay_ms(1_u32);
spisel.set_low().unwrap(); spisel.set_low().unwrap();
// Create SPI1 for HAL // Create SPI1 for HAL
@ -153,11 +159,11 @@ const APP: () = {
enc424j600::spi::interfaces::SPI_MODE, enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
clocks); clocks);
enc424j600::SpiEth::new(spi_eth_port, spi1_nss) enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay)
}; };
// Init controller // Init controller
match spi_eth.init_dev(&mut delay) { match spi_eth.init_dev() {
Ok(_) => { Ok(_) => {
iprintln!(stim0, "Initializing Ethernet...") iprintln!(stim0, "Initializing Ethernet...")
} }
@ -168,7 +174,7 @@ const APP: () = {
// Read MAC // Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6]; let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_from_mac(&mut eth_mac_addr); spi_eth.read_from_mac(&mut eth_mac_addr).unwrap();
for i in 0..6 { for i in 0..6 {
let byte = eth_mac_addr[i]; let byte = eth_mac_addr[i];
match i { match i {
@ -180,8 +186,8 @@ const APP: () = {
} }
// Init Rx/Tx buffers // Init Rx/Tx buffers
spi_eth.init_rxbuf(); spi_eth.init_rxbuf().unwrap();
spi_eth.init_txbuf(); spi_eth.init_txbuf().unwrap();
iprintln!(stim0, "Ethernet controller initialized"); iprintln!(stim0, "Ethernet controller initialized");
// Init smoltcp interface // Init smoltcp interface
@ -205,7 +211,7 @@ const APP: () = {
// Setup SysTick after releasing SYST from Delay // Setup SysTick after releasing SYST from Delay
// Reference to stm32-eth:examples/ip.rs // Reference to stm32-eth:examples/ip.rs
timer_setup(delay.free(), clocks); timer_setup(hal_delay.free(), clocks);
iprintln!(stim0, "Timer initialized"); iprintln!(stim0, "Timer initialized");
init::LateResources { init::LateResources {

21
examples/tx_stm32f407.rs
View File

@ -20,6 +20,9 @@ use stm32f4xx_hal::{
use enc424j600; use enc424j600;
use enc424j600::EthController; use enc424j600::EthController;
mod delay;
use delay::AsmDelay;
/// ///
use stm32f4xx_hal::{ use stm32f4xx_hal::{
stm32::SPI1, stm32::SPI1,
@ -30,7 +33,8 @@ use stm32f4xx_hal::{
}; };
type BoosterSpiEth = enc424j600::SpiEth< type BoosterSpiEth = enc424j600::SpiEth<
Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>, Spi<SPI1, (PA5<Alternate<AF5>>, PA6<Alternate<AF5>>, PA7<Alternate<AF5>>)>,
PA4<Output<PushPull>>>; PA4<Output<PushPull>>,
AsmDelay>;
#[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)] #[rtic::app(device = stm32f4xx_hal::stm32, peripherals = true, monotonic = rtic::cyccnt::CYCCNT)]
const APP: () = { const APP: () = {
@ -54,6 +58,7 @@ const APP: () = {
//.pclk2(64.mhz()) //.pclk2(64.mhz())
.require_pll48clk() .require_pll48clk()
.freeze(); .freeze();
let asm_delay = AsmDelay::new(clocks.sysclk().0);
let mut delay = Delay::new(c.core.SYST, clocks); let mut delay = Delay::new(c.core.SYST, clocks);
// Init ITM // Init ITM
@ -82,11 +87,11 @@ const APP: () = {
enc424j600::spi::interfaces::SPI_MODE, enc424j600::spi::interfaces::SPI_MODE,
Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ), Hertz(enc424j600::spi::interfaces::SPI_CLOCK_FREQ),
clocks); clocks);
enc424j600::SpiEth::new(spi_eth_port, spi1_nss) enc424j600::SpiEth::new(spi_eth_port, spi1_nss, asm_delay)
}; };
// Init // Init
match spi_eth.init_dev(&mut delay) { match spi_eth.init_dev() {
Ok(_) => { Ok(_) => {
iprintln!(stim0, "Initializing Ethernet...") iprintln!(stim0, "Initializing Ethernet...")
} }
@ -97,7 +102,7 @@ const APP: () = {
// Read MAC // Read MAC
let mut eth_mac_addr: [u8; 6] = [0; 6]; let mut eth_mac_addr: [u8; 6] = [0; 6];
spi_eth.read_from_mac(&mut eth_mac_addr); spi_eth.read_from_mac(&mut eth_mac_addr).unwrap();
for i in 0..6 { for i in 0..6 {
let byte = eth_mac_addr[i]; let byte = eth_mac_addr[i];
match i { match i {
@ -109,8 +114,8 @@ const APP: () = {
} }
// Init Rx/Tx buffers // Init Rx/Tx buffers
spi_eth.init_rxbuf(); spi_eth.init_rxbuf().unwrap();
spi_eth.init_txbuf(); spi_eth.init_txbuf().unwrap();
iprintln!(stim0, "Ethernet controller initialized"); iprintln!(stim0, "Ethernet controller initialized");
init::LateResources { init::LateResources {
@ -130,7 +135,7 @@ const APP: () = {
0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60, 0x08, 0x00, 0x06, 0x04, 0x00, 0x01, 0x08, 0x60,
0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64, 0x6e, 0x44, 0x42, 0x95, 0xc0, 0xa8, 0x01, 0x64,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xa8,
0x01, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f 0x00, 0x00, 0x00, 0x00, 0x69, 0xd0, 0x85, 0x9f
]; ];
@ -152,7 +157,7 @@ const APP: () = {
_ => () _ => ()
}; };
} }
c.resources.spi_eth.send_raw_packet(&eth_tx_packet); c.resources.spi_eth.send_raw_packet(&eth_tx_packet).unwrap();
iprintln!(stim0, "Packet sent"); iprintln!(stim0, "Packet sent");
c.resources.delay.delay_ms(100_u32); c.resources.delay.delay_ms(100_u32);
} }