init: use delay from internal spi
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@ -67,6 +67,7 @@ impl <SPI: Transfer<u8>,
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impl <SPI: Transfer<u8>,
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NSS: OutputPin,
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Delay: DelayUs<u16>> EthController for SpiEth<SPI, NSS, Delay> {
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fn init_dev(&mut self) -> Result<(), EthControllerError> {
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// Write 0x1234 to EUDAST
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self.spi_port.write_reg_16b(spi::addrs::EUDAST, 0x1234)?;
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// Verify that EUDAST is 0x1234
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@ -83,14 +84,14 @@ impl <SPI: Transfer<u8>,
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let econ2 = self.spi_port.read_reg_8b(spi::addrs::ECON2)?;
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self.spi_port.write_reg_8b(spi::addrs::ECON2, 0x10 | (econ2 & 0b11101111))?;
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// Wait for 25us
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delay.delay_us(25_u16);
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self.spi_port.delay_us(25_u16);
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// Verify that EUDAST is 0x0000
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eudast = self.spi_port.read_reg_16b(spi::addrs::EUDAST)?;
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if eudast != 0x0000 {
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return Err(EthControllerError::GeneralError)
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}
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// Wait for 256us
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delay.delay_us(256_u16);
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self.spi_port.delay_us(256_u16);
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Ok(())
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}
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