renet
/
ENC424J600
10
1
Fork 1
Code Issues 3 Pull Requests 1 Projects Releases Wiki Activity

spi: Impose stricter NSS timing

fix-spi
Harry Ho 2021-06-03 11:47:38 +08:00
parent 35b7924431
commit ec20970a50
1 changed files with 9 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/spi.rs
View File

@ -195,6 +195,13 @@ impl <SPI: Transfer<u8>,
assert!(buf.len() > data_length); assert!(buf.len() > data_length);
// Enable chip select // Enable chip select
self.nss.set_low(); self.nss.set_low();
match opcode {
opcodes::RCRU | opcodes::WCRU |
opcodes::RRXDATA | opcodes::WGPDATA => {
(self.delay_ns)(50); // >=50ns min. CS_n setup time
}
_ => { }
}
// Start writing to SLAVE // Start writing to SLAVE
buf[0] = opcode; buf[0] = opcode;
let result = self.spi.transfer(&mut buf[..data_length+1]); let result = self.spi.transfer(&mut buf[..data_length+1]);
@ -202,9 +209,9 @@ impl <SPI: Transfer<u8>,
opcodes::RCRU | opcodes::WCRU | opcodes::RCRU | opcodes::WCRU |
opcodes::RRXDATA | opcodes::WGPDATA => { opcodes::RRXDATA | opcodes::WGPDATA => {
// Disable chip select // Disable chip select
(self.delay_ns)(60); (self.delay_ns)(50); // >=50ns min. CS_n hold time
self.nss.set_high(); self.nss.set_high();
(self.delay_ns)(30); (self.delay_ns)(20); // >=20ns min. CS_n disable time
} }
_ => { } _ => { }
} }