From ec20970a50db5dd5b923d5715112d0d1eb5df192 Mon Sep 17 00:00:00 2001
From: Harry Ho <hh@m-labs.hk>
Date: Thu, 3 Jun 2021 11:47:38 +0800
Subject: [PATCH] spi: Impose stricter NSS timing

---
 src/spi.rs | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/spi.rs b/src/spi.rs
index d9cd5cf..4484719 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -195,6 +195,13 @@ impl <SPI: Transfer<u8>,
         assert!(buf.len() > data_length);
         // Enable chip select
         self.nss.set_low();
+        match opcode {
+            opcodes::RCRU | opcodes::WCRU |
+            opcodes::RRXDATA | opcodes::WGPDATA => {
+                (self.delay_ns)(50);    // >=50ns min. CS_n setup time
+            }
+            _ => { }
+        }
         // Start writing to SLAVE
         buf[0] = opcode;
         let result = self.spi.transfer(&mut buf[..data_length+1]);
@@ -202,9 +209,9 @@ impl <SPI: Transfer<u8>,
             opcodes::RCRU | opcodes::WCRU |
             opcodes::RRXDATA | opcodes::WGPDATA => {
                 // Disable chip select
-                (self.delay_ns)(60);
+                (self.delay_ns)(50);    // >=50ns min. CS_n hold time
                 self.nss.set_high();
-                (self.delay_ns)(30);
+                (self.delay_ns)(20);    // >=20ns min. CS_n disable time
             }
             _ => { }
         }