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spi: add CS delay

This commit is contained in:
occheung 2021-01-18 15:33:27 +08:00
parent c4b62cc238
commit 26dabd4dc0
1 changed files with 4 additions and 0 deletions
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4
src/spi.rs
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@ -131,13 +131,17 @@ impl <SPI: Transfer<u8>,
match self.spi.transfer(&mut buf) {
Ok(_) => {
// Disable chip select
cortex_m::asm::delay(10_u32);
self.nss.set_high();
cortex_m::asm::delay(5_u32);
Ok(buf[2])
},
// TODO: Maybe too naive?
Err(_) => {
// Disable chip select
cortex_m::asm::delay(10_u32);
self.nss.set_high();
cortex_m::asm::delay(5_u32);
Err(SpiPortError::TransferError)
}
}