From 26dabd4dc04214cb9f44ce098fcaf99c7174f36d Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Mon, 18 Jan 2021 15:33:27 +0800
Subject: [PATCH] spi: add CS delay

---
 src/spi.rs | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/spi.rs b/src/spi.rs
index 58c064b..c2f5dcc 100644
--- a/src/spi.rs
+++ b/src/spi.rs
@@ -131,13 +131,17 @@ impl <SPI: Transfer<u8>,
         match self.spi.transfer(&mut buf) {
             Ok(_) => {
                 // Disable chip select
+                cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
+                cortex_m::asm::delay(5_u32);
                 Ok(buf[2])
             },
             // TODO: Maybe too naive?
             Err(_) => {
                 // Disable chip select
+                cortex_m::asm::delay(10_u32);
                 self.nss.set_high();
+                cortex_m::asm::delay(5_u32);
                 Err(SpiPortError::TransferError)
             }
         }