zynq-rs/src/zynq
Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
2019-10-27 20:30:56 +01:00
..
ddr zynq::ddr, main: parameters, memtest 2019-10-25 23:19:34 +02:00
eth move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
uart move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
axi_gp.rs add zynq::axi_gp 2019-10-19 01:46:43 +02:00
axi_hp.rs add zynq::axi_hp 2019-10-18 23:46:00 +02:00
clocks.rs zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage 2019-10-27 20:30:56 +01:00
mod.rs move slcr, clocks, uart, eth into src/zynq/ 2019-10-21 22:19:03 +02:00
slcr.rs zynq::slcr: doc, fix 2019-10-25 23:18:18 +02:00