Bare-metal Rust on the Xilinx Zynq ZC706 devkit

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Astro 27114aec62 zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage this seems to make DDR RAM work.		2019-10-27 20:30:56 +01:00
.cargo	define custom target, use with cargo-xbuild	2019-08-06 22:03:04 +02:00
openocd	openocd: fix PL_TAPID for both targets	2019-09-28 23:53:40 +02:00
src	zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage	2019-10-27 20:30:56 +01:00
Cargo.lock	Cargo.toml: use compiler_builtins release	2019-09-26 17:54:05 +02:00
Cargo.toml	Cargo.toml: use compiler_builtins release	2019-09-26 17:54:05 +02:00
README.md	README: fix openocd not finding files	2019-08-20 13:45:50 +08:00
armv7-none-eabihf.json	define custom target, use with cargo-xbuild	2019-08-06 22:03:04 +02:00
build.rs	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00
channel-rust-nightly.toml	default.nix: add a static channel-rust-nightly.toml that fits the current rustcSrc	2019-09-26 17:17:31 +02:00
default.nix	default.nix: fix use of rustManifest	2019-09-26 23:34:06 +02:00
link.x	link.x: fix __stack_start	2019-09-29 01:38:47 +02:00
qemu.gdb	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00
runner.sh	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00
shell.nix	default.nix: build zc706	2019-09-26 17:54:37 +02:00

Build

nix-shell --command "cargo xbuild --release"

Debug

Tested with the ZC706 board.

Run the Xilinx Microprocessor Debugger:

/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64/xmd

Connect to target (given it is connected and you have permissions):

connect arm hw

Leave xmd running.

Start the Xilinx version of the GNU debugger with your latest build:

/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin/arm-xilinx-linux-gnueabi-gdb zc706

Connect the debugger to xmd over TCP on localhost:

target remote :1234

Proceed using gdb with load, c

nix-shell --command "cargo xbuild --release"
cd openocd
openocd -f zc706.cfg

nix-shell --command "cargo xbuild --release --no-default-features --features=target_cora_z7_10"
cd openocd
openocd -f cora-z7-10.cfg