|
|
da60be38b1
|
libboard_zynq::flash: move man_start_com(true) into wait_tx_fifo_flush()
|
2019-12-22 03:13:38 +01:00 |
|
|
|
6c4b07e0cf
|
libboard_zynq::flash: syntax
|
2019-12-22 03:12:53 +01:00 |
|
|
|
4439a64974
|
libboard_zc706: move main.rs into experiments bin crate
|
2019-12-18 00:06:10 +01:00 |
|
|
|
cf1983e543
|
split into lib{register, cortex_a9, board_zynq, board_zc706} crates
|
2019-12-17 23:35:58 +01:00 |
|
|
|
1036ecc0f7
|
main: add latest experimentation code
|
2019-12-17 01:09:07 +01:00 |
|
|
|
a8cb085a25
|
cortex_a9::mmu: make OCM region cachable
|
2019-12-17 00:56:18 +01:00 |
|
|
|
1ba587ccf9
|
remove dependency compiler_builtins
no longer required.
|
2019-12-17 00:54:23 +01:00 |
|
|
|
62ecb5095b
|
Cargo.toml: optimize for size
Space in OCM is precious.
|
2019-12-17 00:54:23 +01:00 |
|
|
|
887627b137
|
panic: print location info + message
|
2019-12-17 00:54:20 +01:00 |
|
|
|
0adb0d5c51
|
zynq::flash: remove post-WRDI check
|
2019-12-16 00:49:29 +01:00 |
|
|
|
dd0fe054d7
|
zynq::flash: add working erase(), add barely working program()
|
2019-12-16 00:48:39 +01:00 |
|
|
|
1dbb358a4c
|
zynq::flash::spi_flash_register: doc, add BA
|
2019-12-16 00:46:53 +01:00 |
|
|
|
b94afa1581
|
zynq::flash: add read_reg_until()
|
2019-12-15 23:56:16 +01:00 |
|
|
|
0d1cf04a34
|
zynq::flash: split into mod transfer
|
2019-12-15 19:28:55 +01:00 |
|
|
|
8a9dde6119
|
zynq::flash: add consts
|
2019-12-14 01:57:51 +01:00 |
|
|
|
5268839467
|
zynq::flash: add write_enabled()
|
2019-12-14 01:56:49 +01:00 |
|
|
|
0b9a150255
|
zynq::flash: abstract SpiFlashRegister
|
2019-12-14 01:55:17 +01:00 |
|
|
|
2d1c8e1f4f
|
zynq::flash: fix txd[123] alignment
|
2019-12-14 01:07:15 +01:00 |
|
|
|
e1068af948
|
zynq::flash: add rdsr1()
|
2019-12-12 01:02:09 +01:00 |
|
|
|
3b3b5dc7c1
|
zynq::flash: add support for writing 1/2/3-byte words
|
2019-12-12 00:17:34 +01:00 |
|
|
|
70d56d2b28
|
zynq::flash: doc
|
2019-12-12 00:13:02 +01:00 |
|
|
|
b346ea8297
|
zynq::flash: fix INST_RDCR
|
2019-12-12 00:11:42 +01:00 |
|
|
|
e9b80eaef9
|
zynq::flash: don't send excess data, fixes, refactorings
|
2019-12-10 02:50:44 +01:00 |
|
|
|
0823a74164
|
zynq::flash: fix rx_thres register
|
2019-12-10 02:46:25 +01:00 |
|
|
|
aab82f6843
|
zynq::flash: enable big endian mode
|
2019-12-10 02:45:05 +01:00 |
|
|
|
f3676c945a
|
zynq::flash: flush after instruction
|
2019-12-07 02:48:55 +01:00 |
|
|
|
1e465250f5
|
zynq::flash: enable/disable spi for every transfer
|
2019-12-07 02:11:50 +01:00 |
|
|
|
e37659e4b3
|
zynq::flash: refactor
|
2019-12-05 01:18:52 +01:00 |
|
|
|
45cc271735
|
zynq::flash: fix + refactor
|
2019-12-05 00:05:34 +01:00 |
|
|
|
cfaa1213e2
|
zynq::flash: add more initialization
|
2019-12-03 02:41:49 +01:00 |
|
|
|
7107244a6e
|
zynq::flash: start implementing Manual mode
|
2019-11-30 02:48:39 +01:00 |
|
|
|
dd3ad3be67
|
zynq::flash: implement stopping LinearAddressing mode
|
2019-11-29 23:48:08 +01:00 |
|
|
|
a8a7f11990
|
zynq::flash: configure quad i/o fast read mode
|
2019-11-29 23:37:54 +01:00 |
|
|
|
78caca1f04
|
zynq::flash: setup additional signals
|
2019-11-28 03:22:26 +01:00 |
|
|
|
5642feb824
|
zynq::flash: add missing config bits to enable addressing mode
|
2019-11-28 03:02:51 +01:00 |
|
|
|
a199a5dc7d
|
zynq::flash: add more setup
|
2019-11-23 01:59:24 +01:00 |
|
|
|
3180f1c3f7
|
zynq::flash: begin driver implementation
|
2019-11-21 00:14:09 +01:00 |
|
|
|
8037042040
|
zynq::slcr: implement boot_mode bits
|
2019-11-20 21:31:54 +01:00 |
|
|
|
6ffcf7d4a4
|
ram: lock for concurrent use
this may be reverted if ram allocation shall be more separate.
|
2019-11-20 17:25:54 +01:00 |
|
|
|
4f8a76e29b
|
stdio: lock for use by core1
|
2019-11-20 17:00:57 +01:00 |
|
|
|
ff41f4dd2d
|
cortex_a9::mutex: restore and fix powersaving behaviour, doc
|
2019-11-20 16:30:56 +01:00 |
|
|
|
d89f594ba4
|
cortex_a9::mutex: use AtomU32, remove powersaving behavior
Mutex works properly now.
|
2019-11-18 02:37:59 +01:00 |
|
|
|
4e4ff512d9
|
add cortex_a9::mutex
|
2019-11-18 02:13:54 +01:00 |
|
|
|
85f29ace6b
|
boot: flush cache-line
|
2019-11-18 01:22:57 +01:00 |
|
|
|
ef6d0ff3f1
|
boot: reset core1 before start
|
2019-11-18 00:38:03 +01:00 |
|
|
|
0bc941d789
|
main: start_core1
|
2019-11-16 00:53:30 +01:00 |
|
|
|
a416f48af1
|
main: add empty main_core1()
|
2019-11-16 00:21:57 +01:00 |
|
|
|
b6596d930d
|
boot: ACTLR.enable_smp()
|
2019-11-16 00:12:58 +01:00 |
|
|
|
49901d1b8a
|
boot: prepare core1 bootup
|
2019-11-15 23:59:01 +01:00 |
|
Björn Stein
|
4a1d0fc0c3
|
zynq::mpcore: add register definitions
|
2019-11-14 02:11:58 +01:00 |
|
