forked from M-Labs/zynq-rs
zynq::ddr: fix PLL_FDIV_LOCK_PARAM usage
this seems to make DDR RAM work.
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@ -102,7 +102,7 @@ impl CpuClocks {
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);
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);
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.last()
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.nth(0)
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.expect("PLL_FDIV_LOCK_PARAM")
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.expect("PLL_FDIV_LOCK_PARAM")
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.1.clone();
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.1.clone();
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regs.ddr_pll_cfg.write(
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regs.ddr_pll_cfg.write(
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