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535 Commits

Author SHA1 Message Date
pca006132 84041a3154 libsupport_zynq/ram: use core0 allocator by default. 2020-08-03 14:48:44 +08:00
pca006132 5850401d72 libsupport_zynq/ram: split allocators for two cores. 2020-08-03 14:48:44 +08:00
pca006132 ccce37dffd linked_list_allocator: upgraded to 0.8.4 
So we get the `used` function to check heap usage.
 2020-08-03 14:48:17 +08:00
pca006132 3bbd1513fb build.sh: specify build experiments 
Otherwise we cannot turn off the default feature for libsupport_zynq.
https://github.com/rust-lang/cargo/issues/8366#issuecomment-644995218
 2020-08-03 14:09:36 +08:00
pca006132 7d38c53c18 libsupport_zynq/abort: moved core1 restart code to user code. 2020-08-03 14:09:36 +08:00
pca006132 02a2c4d1e3 experiments: updated example. 2020-08-03 12:35:17 +08:00
pca006132 12669124a4 libcortex_a9/mutex: added interrupt critical section mask. 2020-08-03 12:35:17 +08:00
pca006132 8f0a6bd5ea libsupport_zynq/abort: restart core1 main on core1 IRQ#0. 2020-08-03 12:35:17 +08:00
pca006132 c1f61b5673 libcortex_a9/boot: enable IRQ on reset. 2020-08-03 12:35:17 +08:00
pca006132 2927c43309 libboard_zynq/gic: refactored and added SGI functions. 2020-08-03 12:35:17 +08:00
Astro 187801c4a7 gic: start implementation 2020-08-03 12:35:17 +08:00
pca006132 91ece367f2 libboard_zynq/mpcore: added generated register definitions 2020-08-03 12:35:17 +08:00
Astro 1f05e6977e eth::phy: replace ExtendedStatus with PSSR 2020-07-29 21:49:18 +02:00
Astro e408a8b22d eth::phy::extended_status: fix cap_1000base_x_full() bit position 2020-07-29 21:29:28 +02:00
Astro 27effb6257 eth::phy: s/Marvel/Marvell/ 2020-07-29 20:08:38 +02:00
Astro de5f605d60 eth: refactor peripheral instance into type parameter, improve clock setup 2020-07-29 19:45:01 +02:00
pca006132 ad47521e4b libsupport_zynq/boot: fixed core1 disable. 2020-07-28 12:36:23 +08:00
pca006132 c50e72f91e experiments: use OCM instead of OCM3 (#54) 2020-07-28 12:36:23 +08:00
pca006132 b099c56569 libcortex_a9/sync_channel: new version compiled. 2020-07-28 12:36:16 +08:00
Astro ef4fb598fb ddr: improve dci divisors calculation 2020-07-28 00:43:33 +02:00
Astro 0aa75d3544 experiments: fix timer.get_us() usage 2020-07-22 23:47:57 +02:00
Astro f36b1a610e timer::global: wrap us in Microseconds, impl embedded_hal blocking delay traits 2020-07-22 23:41:15 +02:00
Astro 7f45d10af3 timer::global::CountDown: fix delaying from "up to" to "at least" the timespan 2020-07-22 22:43:10 +02:00
Astro 855d94c48e dmac: remove unused module 2020-07-20 19:42:32 +02:00
Sebastien Bourdeauducq 84f1380f48 libasync: assert that callback consumes data in smoltcp recv 2020-07-19 16:14:29 +08:00
Sebastien Bourdeauducq f8785c3f07 fix some compilation warnings 2020-07-19 15:39:08 +08:00
Sebastien Bourdeauducq 7b78bc0494 libasync: new stream.recv API 
M-Labs/artiq-zynq#40 (comment)
 2020-07-19 15:34:32 +08:00
Sebastien Bourdeauducq ef88a1313a shell.nix: remove gcc 2020-07-19 15:34:18 +08:00
Astro 484e385160 eth: implement DeviceCapabilities.max_burst_size 
this is a hint that /could/ boost TCP performance.
 2020-07-16 00:17:13 +02:00
pca006132 074438c3c7 libcortex_a9: added `try_lock` for mutex. 2020-07-15 16:44:01 +08:00
Astro 191abf6b8f mpidr: wrap with proper bitfield getters 
Prevents callers from dealing with CORE_MASK.
 2020-07-08 00:04:54 +02:00
Sebastien Bourdeauducq 371e59cef5 libboard_zynq: add fpgax_clk_ctrl registers 2020-07-07 19:37:51 +08:00
pca006132 e67efe439b libsupport: fixed core1 restart. 
The TRM mentioned that user should stop the clock, de-assert the reset,
and then restart the clock for core reset.

This fixes the kernel restart problem in one of the zc706 board.
 2020-07-07 10:17:15 +08:00
Astro e4e7141bf3 ddr: delint 2020-07-06 19:46:18 +02:00
Sebastien Bourdeauducq f68b5896ce remove unused imports 2020-07-06 21:03:36 +08:00
Sebastien Bourdeauducq e430600683 fix exception vectors 2020-07-06 21:02:46 +08:00
Sebastien Bourdeauducq 0c60d684e4 slcr: remove soft reset 
Does not work and probably difficult to get to work.
 2020-07-06 13:06:10 +08:00
Sebastien Bourdeauducq 6fa3a6bbd9 fix previous commit 2020-07-06 12:11:20 +08:00
Sebastien Bourdeauducq 7082e07a18 experiments: move BSS and stack to OCM3 2020-07-06 11:57:02 +08:00
Sebastien Bourdeauducq 21c0c5cbc8 Revert "simplify ps7_init" 
What the simplified ps7_init does can now be reproduced by the DDRC driver.
On the other hand, we are still experiencing crazy Zynq instability issues, so keep the original ps7_init around for debugging.

This reverts commit 9fcf9243f2.
 2020-07-06 11:55:04 +08:00
pca006132 90904634cd DDR: fixed register write. 
Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.
 2020-07-06 11:46:37 +08:00
Sebastien Bourdeauducq ae4d3e2455 smoltcp: enable IPv6 2020-07-06 11:30:48 +08:00
Sebastien Bourdeauducq 9fcf9243f2 simplify ps7_init 2020-07-06 00:52:40 +08:00
pca006132 90e33f688a FPU: moved enable function to zc706 2020-07-03 16:02:34 +08:00
Astro f0697c3ec3 ddr: implement additional configuration 2020-07-03 02:20:10 +02:00
Astro b2c707d543 ddr: remove superfluous `_reg` from register names 2020-07-03 02:20:10 +02:00
pca006132 6195ad40c3 libsupport_zynq: make panic handler an optional feature 2020-06-29 10:05:46 +08:00
Sebastien Bourdeauducq dd288912af fix experiments build for Cora 2020-06-28 17:47:33 +08:00
Astro ec252b099c experiments: don't write raw blocks to the sdcard by default 2020-06-26 23:27:28 +02:00
Astro a16c639eaf experiments: add bandwidth tester 2020-06-26 22:36:52 +02:00