24 Commits

Author	SHA1	Message	Date
Astro	b8818863c4	read clocks	2019-08-17 03:20:04 +02:00
Astro	1f9ad5ff62	delint	2019-08-11 00:56:54 +02:00
Astro	b9c233b05b	compile fixes	2019-07-01 00:15:17 +02:00
Astro	d6b2321fee	eth: fix mio_pin setup	2019-06-29 00:00:22 +02:00
Astro	9ab40daca2	eth: setup_gem0/1_clock()	2019-06-25 21:50:38 +02:00
Astro	5823d90db1	phy: implement control, status, reset	2019-06-25 21:48:47 +02:00
Astro	ce74fe7299	eth: prepare tx	2019-06-22 01:39:44 +02:00
Astro	ec5dda4d0a	eth: add const MTU	2019-06-22 01:34:17 +02:00
Astro	6757ceb76c	eth rx: error handling	2019-06-22 01:20:18 +02:00
Astro	a4be03bee9	rx: PktRef	2019-06-21 01:19:04 +02:00
Astro	e5881a14ad	eth rx: descriptors/buffers as refs ... avoid moving these after their addresses have been written to the qbar	2019-06-21 00:58:18 +02:00
Astro	54d0f3583d	eth: fix io configuration ... phy detection now works	2019-06-18 23:10:35 +02:00
Astro	81a892b618	eth: recv_next()	2019-06-10 02:44:29 +02:00
Astro	f92ea3b99d	eth: start_tx	2019-06-09 20:28:33 +02:00
Astro	f07a541c99	eth: model rx/tx state with type parameters	2019-06-09 20:10:41 +02:00
Astro	74bd81f87f	eth: add safety asserts	2019-06-09 02:23:37 +02:00
Astro	824e91e6cb	eth: rx/tx desc list, start_rx	2019-06-09 01:02:10 +02:00
Astro	b9ca9324f0	eth: fix initialization	2019-06-04 23:48:33 +02:00
Astro	b13bf72c17	eth: begin phy communication	2019-05-30 02:42:42 +02:00
Astro	c0610ad66a	slcr: init gem* rclk/clk	2019-05-30 02:26:19 +02:00
Astro	d10ffe9eb9	eth: setup mio_pins, configure net_cfg	2019-05-25 03:06:39 +02:00
Astro	402b8c9ab1	eth: no unsafe, note, add qbar register fields	2019-05-23 23:18:36 +02:00
Astro	785e726661	RegisterW/RegisterRW: required &mut self for safety	2019-05-23 18:01:18 +02:00
Astro	b754581452	eth: add regs and init	2019-05-07 19:28:33 +02:00