forked from M-Labs/zynq-rs
zynq::ddr: fix clock setup
This commit is contained in:
parent
f199ac68b4
commit
fc39885d3b
10
src/main.rs
10
src/main.rs
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@ -87,16 +87,6 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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fn main() {
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fn main() {
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println!("Main.");
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println!("Main.");
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zynq::clocks::CpuClocks::enable_ddr(1_066_666_666);
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let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read();
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println!("PLLs: {}", pll_status);
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let clocks = zynq::clocks::CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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println!("CPU speeds: {}/{}/{}/{} MHz",
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clocks.cpu_6x4x() / 1_000_000,
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let mut ddr = zynq::ddr::DdrRam::new();
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let mut ddr = zynq::ddr::DdrRam::new();
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println!("DDR: {:?}", ddr.status());
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println!("DDR: {:?}", ddr.status());
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ddr.memtest();
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ddr.memtest();
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@ -10,8 +10,8 @@ mod regs;
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const DDR_FREQ: u32 = 666_666_666;
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const DDR_FREQ: u32 = 666_666_666;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
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const DDR_FREQ: u32 = 800_000_000;
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const DDR_FREQ: u32 = 533_333_333;
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/// MT41K256M16HA-125
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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const DCI_FREQ: u32 = 10_000_000;
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@ -22,8 +22,7 @@ pub struct DdrRam {
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impl DdrRam {
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impl DdrRam {
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pub fn new() -> Self {
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pub fn new() -> Self {
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let clocks = CpuClocks::get();
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let clocks = Self::clock_setup();
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Self::clock_setup(&clocks);
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Self::calibrate_iob_impedance(&clocks);
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Self::calibrate_iob_impedance(&clocks);
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Self::configure_iob();
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Self::configure_iob();
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@ -35,8 +34,10 @@ impl DdrRam {
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup(clocks: &CpuClocks) {
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fn clock_setup() -> CpuClocks {
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CpuClocks::enable_ddr(1_066_666_666);
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let clocks = CpuClocks::get();
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CpuClocks::enable_ddr(clocks.cpu);
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let clocks = CpuClocks::get();
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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@ -50,6 +51,7 @@ impl DdrRam {
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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.ddr_3xclk_divisor(ddr3x_clk_divisor)
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);
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);
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});
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});
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clocks
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}
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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@ -57,7 +59,7 @@ impl DdrRam {
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fn calibrate_iob_impedance(clocks: &CpuClocks) {
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fn calibrate_iob_impedance(clocks: &CpuClocks) {
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let divisor0 = (clocks.ddr / DCI_FREQ)
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let divisor0 = (clocks.ddr / DCI_FREQ)
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.max(1).min(63) as u8;
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.max(1).min(63) as u8;
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let divisor1 = (clocks.ddr / DCI_FREQ / u32::from(divisor0))
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let divisor1 = 1 + (clocks.ddr / DCI_FREQ / u32::from(divisor0))
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.max(1).min(63) as u8;
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.max(1).min(63) as u8;
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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@ -76,7 +78,7 @@ impl DdrRam {
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slcr.ddriob_dci_ctrl.modify(|_, w|
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.reset(true)
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w.reset(true)
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);
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);
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// Step 3.b. for DDR3
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// Step 3.b. for DDR3/DDR3L
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slcr.ddriob_dci_ctrl.modify(|_, w|
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slcr.ddriob_dci_ctrl.modify(|_, w|
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w.nref_opt1(0)
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w.nref_opt1(0)
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.nref_opt2(0)
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.nref_opt2(0)
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