forked from M-Labs/zynq-rs
delint
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@ -1,4 +1,4 @@
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use libregister::{RegisterR, RegisterW, RegisterRW};
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use libregister::{RegisterR, RegisterRW};
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use super::slcr;
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use super::slcr;
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pub use slcr::ArmPllSource;
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pub use slcr::ArmPllSource;
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@ -1,5 +1,3 @@
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use core::fmt;
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use libregister::*;
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use libregister::*;
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mod regs;
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mod regs;
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@ -1,5 +1,3 @@
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use volatile_register::{RO, WO, RW};
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use libregister::{
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use libregister::{
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register, register_at,
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register, register_at,
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register_bit, register_bits, register_bits_typed,
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register_bit, register_bits, register_bits_typed,
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@ -29,8 +29,6 @@ const INST_WRDI: u8 = 0x04;
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const INST_WREN: u8 = 0x06;
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const INST_WREN: u8 = 0x06;
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/// Instruction: Program page
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/// Instruction: Program page
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const INST_PP: u8 = 0x02;
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const INST_PP: u8 = 0x02;
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/// Instruction: Sector Erase
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const INST_SE: u8 = 0xD8;
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/// Instruction: Erase 4K Block
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/// Instruction: Erase 4K Block
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const INST_BE_4K: u8 = 0x20;
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const INST_BE_4K: u8 = 0x20;
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@ -93,18 +91,6 @@ impl<MODE> Flash<MODE> {
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);
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);
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}
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}
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fn enable_interrupts(&mut self) {
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self.regs.intr_en.write(
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regs::IntrEn::zeroed()
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.rx_overflow(true)
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.tx_fifo_not_full(true)
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.tx_fifo_full(true)
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.rx_fifo_not_empty(true)
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.rx_fifo_full(true)
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.tx_fifo_underflow(true)
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);
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}
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fn clear_rx_fifo(&self) {
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fn clear_rx_fifo(&self) {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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while self.regs.intr_status.read().rx_fifo_not_empty() {
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let _ = self.regs.rx_data.read();
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let _ = self.regs.rx_data.read();
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