forked from M-Labs/zynq-rs
eth rx: descriptors/buffers as refs
avoid moving these after their addresses have been written to the qbar
This commit is contained in:
parent
d65398205f
commit
e5881a14ad
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@ -290,8 +290,8 @@ impl<RX, TX> Eth<RX, TX> {
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self.regs.dma_cfg.write(
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self.regs.dma_cfg.write(
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regs::DmaCfg::zeroed()
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regs::DmaCfg::zeroed()
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// 1600 bytes
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// 1536 bytes
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.ahb_mem_rx_buf_size(0x19)
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.ahb_mem_rx_buf_size(0x18)
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// 8 KB
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// 8 KB
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.rx_pktbuf_memsz_sel(0x3)
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.rx_pktbuf_memsz_sel(0x3)
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// 4 KB
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// 4 KB
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@ -306,37 +306,23 @@ impl<RX, TX> Eth<RX, TX> {
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self.regs.net_ctrl.write(
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self.regs.net_ctrl.write(
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regs::NetCtrl::zeroed()
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regs::NetCtrl::zeroed()
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.mgmt_port_en(true)
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.mgmt_port_en(true)
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.tx_en(true)
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.rx_en(true)
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);
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);
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}
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}
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pub fn start_rx<'rx>(self, rx_buffers: [&'rx mut [u8]; rx::DESCS]) -> Eth<rx::DescList<'rx>, TX> {
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pub fn start_rx<'rx>(self, list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; 1536]]) -> Eth<rx::DescList<'rx>, TX> {
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let new_self = Eth {
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let new_self = Eth {
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regs: self.regs,
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regs: self.regs,
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rx: rx::DescList::new(rx_buffers),
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rx: rx::DescList::new(list, rx_buffers),
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tx: self.tx,
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tx: self.tx,
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};
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};
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let list_addr = &new_self.rx as *const _ as u32;
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let list_addr = new_self.rx.list_addr();
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assert!(list_addr & 0b11 == 0);
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assert!(list_addr & 0b11 == 0);
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new_self.regs.rx_qbar.write(
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new_self.regs.rx_qbar.write(
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regs::RxQbar::zeroed()
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regs::RxQbar::zeroed()
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.rx_q_baseaddr(list_addr >> 2)
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.rx_q_baseaddr(list_addr >> 2)
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);
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);
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new_self
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new_self.regs.net_ctrl.modify(|_, w|
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}
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w.rx_en(true)
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pub fn start_tx<'tx>(self, tx_buffers: [&'tx [u8]; tx::DESCS]) -> Eth<RX, tx::DescList<'tx>> {
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let new_self = Eth {
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regs: self.regs,
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rx: self.rx,
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tx: tx::DescList::new(tx_buffers),
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};
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let list_addr = &new_self.tx as *const _ as u32;
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assert!(list_addr & 0b11 == 0);
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new_self.regs.tx_qbar.write(
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regs::TxQbar::zeroed()
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.tx_q_baseaddr(list_addr >> 2)
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);
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);
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new_self
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new_self
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}
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}
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@ -240,7 +240,9 @@ register_bit!(dma_cfg, ahb_endian_swp_pkt_en, 7);
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register_bits!(dma_cfg, rx_pktbuf_memsz_sel, u8, 8, 9);
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register_bits!(dma_cfg, rx_pktbuf_memsz_sel, u8, 8, 9);
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register_bit!(dma_cfg, tx_pktbuf_memsz_sel, 10);
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register_bit!(dma_cfg, tx_pktbuf_memsz_sel, 10);
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register_bit!(dma_cfg, csum_gen_offload_en, 11);
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register_bit!(dma_cfg, csum_gen_offload_en, 11);
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register_bits!(dma_cfg, ahb_mem_rx_buf_size, u8, 16, 23);
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register_bits!(dma_cfg,
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/// 64 bytes unit
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ahb_mem_rx_buf_size, u8, 16, 23);
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register_bit!(dma_cfg, disc_when_no_ahb, 24);
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register_bit!(dma_cfg, disc_when_no_ahb, 24);
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register!(tx_status, TxStatus, RW, u32);
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register!(tx_status, TxStatus, RW, u32);
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@ -3,7 +3,7 @@ use crate::{register, register_bit, register_bits, register_bits_typed, regs::*}
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/// Descriptor entry
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/// Descriptor entry
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#[repr(C)]
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#[repr(C)]
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struct DescEntry {
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pub struct DescEntry {
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word0: DescWord0,
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word0: DescWord0,
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word1: DescWord1,
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word1: DescWord1,
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}
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}
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@ -32,40 +32,43 @@ register_bit!(desc_word1, uni_hash_match, 29);
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register_bit!(desc_word1, multi_hash_match, 30);
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register_bit!(desc_word1, multi_hash_match, 30);
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register_bit!(desc_word1, global_broadcast, 31);
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register_bit!(desc_word1, global_broadcast, 31);
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/// Number of descriptors
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pub const DESCS: usize = 8;
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#[repr(C)]
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#[repr(C)]
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pub struct DescList<'a> {
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pub struct DescList<'a> {
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list: [DescEntry; DESCS],
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list: &'a mut [DescEntry],
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buffers: [&'a mut [u8]; DESCS],
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buffers: &'a mut [[u8; 1536]],
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next: usize,
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next: usize,
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}
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}
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impl<'a> DescList<'a> {
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impl<'a> DescList<'a> {
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pub fn new(buffers: [&'a mut [u8]; DESCS]) -> Self {
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pub fn new(list: &'a mut [DescEntry], buffers: &'a mut [[u8; 1536]]) -> Self {
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let mut list: [DescEntry; DESCS] = unsafe { uninitialized() };
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let last = list.len().min(buffers.len()) - 1;
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for i in 0..DESCS {
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for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
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assert!(buffers[i].len() >= 1536);
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let is_last = i == last;
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let buffer_addr = &mut buffers[i][0] as *mut _ as u32;
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assert!(buffer.len() >= 1536);
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let buffer_addr = &mut buffer[0] as *mut _ as u32;
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assert!(buffer_addr & 0b11 == 0);
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assert!(buffer_addr & 0b11 == 0);
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list[i].word0.write(
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entry.word0.write(
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DescWord0::zeroed()
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DescWord0::zeroed()
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.used(false)
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.used(false)
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.wrap(i == DESCS - 1)
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.wrap(is_last)
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.address(buffer_addr >> 2)
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.address(buffer_addr >> 2)
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);
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);
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list[i].word1.write(
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entry.word1.write(
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DescWord1::zeroed()
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DescWord1::zeroed()
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);
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);
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}
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}
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DescList {
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DescList {
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list, buffers,
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list,
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buffers,
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next: 0,
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next: 0,
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}
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}
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}
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}
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pub fn list_addr(&self) -> u32 {
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&self.list[0] as *const _ as u32
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}
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pub fn recv_next(&mut self) -> Option<&[u8]> {
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pub fn recv_next(&mut self) -> Option<&[u8]> {
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if self.list[self.next].word0.read().used() {
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if self.list[self.next].word0.read().used() {
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let len = self.list[self.next].word1
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let len = self.list[self.next].word1
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11
src/main.rs
11
src/main.rs
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@ -92,14 +92,9 @@ fn main() {
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}
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}
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}
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}
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let mut rx_buffers = [[0u8; 1536]; eth::rx::DESCS];
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let mut rx_descs: [eth::rx::DescEntry; 8] = unsafe { uninitialized() };
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let mut rx_buffer_ptrs: [&mut [u8]; eth::rx::DESCS] = unsafe {
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let mut rx_buffers = [[0u8; 1536]; 8];
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uninitialized()
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let mut eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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};
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for (i, (ptr, buf)) in rx_buffer_ptrs.iter_mut().zip(rx_buffers.iter_mut()).enumerate() {
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*ptr = buf;
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}
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let mut eth = eth.start_rx(rx_buffer_ptrs);
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loop {
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loop {
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match eth.recv_next() {
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match eth.recv_next() {
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