forked from M-Labs/zynq-rs
standard capacity support
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074b3547de
commit
d3b488bfb3
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@ -205,6 +205,13 @@ impl SdCard {
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self.sdio.set_block_size(512)?;
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self.sdio.set_block_size(512)?;
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}
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}
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let real_addr = if self.hcs {
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address
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} else {
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// standard capacity card uses byte address
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address * 0x200
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};
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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cache::dcci_slice(buffer);
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cache::dcci_slice(buffer);
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@ -230,7 +237,7 @@ impl SdCard {
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};
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};
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self.sdio
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self.sdio
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.cmd_transfer_with_mode(cmd, address, block_cnt, mode)?;
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.cmd_transfer_with_mode(cmd, real_addr, block_cnt, mode)?;
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self.wait_transfer_complete()?;
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self.wait_transfer_complete()?;
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cache::dcci_slice(buffer);
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cache::dcci_slice(buffer);
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@ -258,6 +265,13 @@ impl SdCard {
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self.sdio.set_block_size(512)?;
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self.sdio.set_block_size(512)?;
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}
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}
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let real_addr = if self.hcs {
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address
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} else {
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// standard capacity card uses byte address
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address * 0x200
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};
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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self.adma2_desc_table.setup(&mut self.sdio, block_cnt as u32, buffer);
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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// invalidate D cache, required for ZC706, not sure for Cora Z7 10
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cache::dcci_slice(buffer);
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cache::dcci_slice(buffer);
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@ -281,7 +295,7 @@ impl SdCard {
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};
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};
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self.sdio
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self.sdio
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.cmd_transfer_with_mode(cmd, address, block_cnt, mode)?;
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.cmd_transfer_with_mode(cmd, real_addr, block_cnt, mode)?;
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// wait for transfer complete interrupt
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// wait for transfer complete interrupt
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self.wait_transfer_complete()?;
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self.wait_transfer_complete()?;
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