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zynq-rs
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fix SP init

This commit is contained in:
Astro 2019-05-20 01:21:22 +02:00
parent b754581452
commit c88374eab1
1 changed files with 9 additions and 6 deletions
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15
src/main.rs
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@ -29,15 +29,12 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
use cortex_a9::{asm, regs::*}; use cortex_a9::{asm, regs::*};
const CORE_MASK: u32 = 0x3; const CORE_MASK: u32 = 0x3;
// End of OCM RAM let stack_start = __end + 4096;
const STACK_START: u32 = 256 << 10;
match MPIDR.get() & CORE_MASK { match MPIDR.get() & CORE_MASK {
0 => { 0 => {
SP.set(STACK_START); SP.set(stack_start);
zero_bss(&mut __bss_start, &mut __bss_end); boot_core0();
main();
panic!("return from main");
} }
_ => loop { _ => loop {
// if not core0, infinitely wait for events // if not core0, infinitely wait for events
@ -46,6 +43,12 @@ pub unsafe extern "C" fn _boot_cores() -> ! {
} }
} }
unsafe fn boot_core0() -> ! {
zero_bss(&mut __bss_start, &mut __bss_end);
main();
panic!("return from main");
}
fn main() { fn main() {
let mut uart = Uart::uart0(); let mut uart = Uart::uart0();
writeln!(uart, "Hello World\r").unwrap(); writeln!(uart, "Hello World\r").unwrap();