forked from M-Labs/zynq-rs
zynq::ddr, main: parameters, memtest
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@ -87,6 +87,9 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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fn main() {
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println!("Main.");
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zynq::clocks::CpuClocks::enable_ddr(1_066_000_000);
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let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read();
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println!("PLLs: {}", pll_status);
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let clocks = zynq::clocks::CpuClocks::get();
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println!("Clocks: {:?}", clocks);
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println!("CPU speeds: {}/{}/{}/{} MHz",
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@ -94,7 +97,9 @@ fn main() {
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clocks.cpu_3x2x() / 1_000_000,
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clocks.cpu_2x() / 1_000_000,
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clocks.cpu_1x() / 1_000_000);
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let ddr = zynq::ddr::DdrRam::new();
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let mut ddr = zynq::ddr::DdrRam::new();
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println!("DDR: {:?}", ddr.status());
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ddr.memtest();
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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@ -1,4 +1,4 @@
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use crate::regs::{RegisterR, RegisterRW};
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use super::slcr;
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#[cfg(feature = "target_zc706")]
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@ -90,19 +90,33 @@ impl CpuClocks {
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pll / u32::from(uart_clk_ctrl.divisor())
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}
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 25.10.4 PLLs
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pub fn enable_ddr(target_clock: u32) {
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let fdiv = (target_clock / PS_CLK).min(66) as u16;
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let regs = slcr::RegisterBlock::new();
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(true)
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.pll_bypass_force(true)
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);
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let fdiv = (target_clock / PS_CLK).max(127) as u16;
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_reset(false)
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.pll_fdiv(fdiv)
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);
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.last()
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.expect("PLL_FDIV_LOCK_PARAM")
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.1.clone();
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regs.ddr_pll_cfg.write(
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slcr::PllCfg::zeroed()
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.pll_res(pll_res)
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.pll_cp(pll_cp)
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.lock_cnt(lock_cnt)
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);
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_reset(true)
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);
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_reset(false)
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);
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while ! regs.pll_status.read().ddr_pll_lock() {}
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_bypass_force(false)
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@ -110,3 +124,27 @@ impl CpuClocks {
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);
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}
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}
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/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
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const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[
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(13, (2, 6, 750)),
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(14, (2, 6, 700)),
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(15, (2, 6, 650)),
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(16, (2, 10, 625)),
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(17, (2, 10, 575)),
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(18, (2, 10, 550)),
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(19, (2, 10, 525)),
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(20, (2, 12, 500)),
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(21, (2, 12, 475)),
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(22, (2, 12, 450)),
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(23, (2, 12, 425)),
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(25, (2, 12, 400)),
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(26, (2, 12, 375)),
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(28, (2, 12, 350)),
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(30, (2, 12, 325)),
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(33, (2, 2, 300)),
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(36, (2, 2, 275)),
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(40, (2, 2, 250)),
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(47, (3, 12, 250)),
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(66, (2, 4, 250)),
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];
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@ -1,11 +1,19 @@
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::println;
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use super::slcr;
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use super::clocks::CpuClocks;
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mod regs;
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#[cfg(feature = "target_zc706")]
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/// Micron MT41J256M8HX-15E: 667 MHz DDR3
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const DDR_FREQ: u32 = 666_666_666;
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#[cfg(feature = "target_cora_z7_10")]
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/// Micron MT41K256M16HA-125: 800 MHz DDR3L
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const DDR_FREQ: u32 = 800_000_000;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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pub struct DdrRam {
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@ -131,12 +139,24 @@ impl DdrRam {
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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// Enable internal V[REF]
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#[cfg(feature = "target_zc706")]
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let vref_sel = slcr::DdriobVrefSel::Vref0_75V;
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#[cfg(feature = "target_cora_z7_10")]
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let vref_sel = slcr::DdriobVrefSel::Vref0_675V;
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// // Enable internal V[REF]
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// slcr.ddriob_ddr_ctrl.modify(|_, w| w
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// .vref_ext_en_lower(false)
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// .vref_ext_en_upper(false)
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// .vref_sel(vref_sel)
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// .vref_int_en(true)
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// );
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// Enable external V[REF]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_ext_en_lower(false)
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.vref_ext_en_upper(false)
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.vref_sel(slcr::DdriobVrefSel::Vref0_75V)
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.vref_int_en(true)
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.vref_ext_en_lower(true)
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.vref_ext_en_upper(true)
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.vref_sel(vref_sel)
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.vref_int_en(false)
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);
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});
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}
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@ -158,4 +178,47 @@ impl DdrRam {
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pub fn status(&self) -> regs::ControllerStatus {
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self.regs.mode_sts_reg.read().operating_mode()
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}
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// TODO: move into trait
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pub fn ptr(&mut self) -> *mut u8 {
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// 0x0010_0000 as *mut _
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0x0020_0000 as *mut _
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}
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pub fn size(&self) -> usize {
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// #[cfg(feature = "target_zc706")]
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// 1024 * 1024 * 1024
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4 * 1024 * 1024
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}
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pub fn memtest(&mut self) {
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let slice = unsafe {
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core::slice::from_raw_parts_mut(self.ptr(), self.size())
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};
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let patterns: &'static [u8] = &[0, 0xff, 0x55, 0xaa, 0];
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let mut expected = None;
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for (i, pattern) in patterns.iter().enumerate() {
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println!("memtest phase {} (status: {:?})", i, self.status());
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let slice_len = slice.len();
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let mut progress = 0;
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for (j, b) in slice.iter_mut().enumerate() {
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expected.map(|expected| {
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let read: u8 = *b;
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if read != expected {
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println!("{:08X}: expected {:02X}, read {:02X}", b as *mut u8 as usize, expected, read);
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}
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});
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*b = *pattern;
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// println!("{:08X}", b as *mut u8 as usize);
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let new_progress = 100 * j / slice_len;
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if new_progress > progress {
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progress = new_progress;
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println!("{}%", progress);
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}
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}
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expected = Some(*pattern);
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}
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}
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}
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