forked from M-Labs/zynq-rs
boot: flush cache-line
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commit
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31
src/boot.rs
31
src/boot.rs
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@ -1,7 +1,7 @@
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use r0::zero_bss;
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use r0::zero_bss;
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use vcell::VolatileCell;
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use vcell::VolatileCell;
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::regs::{RegisterR, RegisterW, RegisterRW};
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use crate::cortex_a9::{asm, regs::*, mmu};
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use crate::cortex_a9::{asm, regs::*, cache, mmu};
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use crate::zynq::{slcr, mpcore};
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use crate::zynq::{slcr, mpcore};
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extern "C" {
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extern "C" {
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@ -10,6 +10,7 @@ extern "C" {
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static mut __stack_start: u32;
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static mut __stack_start: u32;
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}
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}
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/// `0` means: wait for initialization by core0
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static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
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static mut CORE1_STACK: VolatileCell<u32> = VolatileCell::new(0);
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#[link_section = ".text.boot"]
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#[link_section = ".text.boot"]
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@ -99,10 +100,12 @@ fn l1_cache_init() {
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dciall();
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dciall();
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}
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}
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pub struct Core1;
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pub struct Core1<S: AsMut<[u32]>> {
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pub stack: S,
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}
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impl Core1 {
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impl<S: AsMut<[u32]>> Core1<S> {
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pub fn stop() {
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pub fn stop(&self) {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(true));
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@ -110,22 +113,32 @@ impl Core1 {
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});
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});
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}
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}
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pub fn start<T: AsMut<[u32]>>(mut stack: T) {
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/// Reset and start core1
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// reset and stop (safe to repeat)
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///
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Self::stop();
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/// The stack must not be in OCM because core1 still has to
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/// initialize its MMU before it can access DDR.
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pub fn start(stack: S) -> Self {
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let mut core = Core1 { stack };
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let stack = stack.as_mut();
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// reset and stop (safe to repeat)
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core.stop();
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let stack = core.stack.as_mut();
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let stack_start = &mut stack[stack.len() - 1];
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let stack_start = &mut stack[stack.len() - 1];
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unsafe {
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unsafe {
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CORE1_STACK.set(stack_start as *mut _ as u32);
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CORE1_STACK.set(stack_start as *mut _ as u32);
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}
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}
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// Ensure stack pointer has been written
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// Ensure stack pointer has been written to cache
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asm::dmb();
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asm::dmb();
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// Flush cache-line
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cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as u32);
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// wake up core1
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// wake up core1
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr::RegisterBlock::unlocked(|slcr| {
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_rst1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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slcr.a9_cpu_rst_ctrl.modify(|_, w| w.a9_clkstop1(false));
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});
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});
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core
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}
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}
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}
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}
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@ -71,6 +71,14 @@ pub fn dccimva(addr: usize) {
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}
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}
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}
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}
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/// clear cache line by virtual address to point of coherency (DCCMVAC)
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#[inline]
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pub fn dccmvac(addr: u32) {
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unsafe {
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asm!("mcr p15, 0, $0, c7, c10, 1" :: "r" (addr) :: "volatile");
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}
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}
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/// The DCCIVMA (data cache clear and invalidate) applied to the
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/// The DCCIVMA (data cache clear and invalidate) applied to the
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/// region of memory occupied by the argument. This does not modify
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/// region of memory occupied by the argument. This does not modify
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/// the argument, but due to the invalidate part (only ever needed if
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/// the argument, but due to the invalidate part (only ever needed if
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