forked from M-Labs/zynq-rs
zynq::ddr: parameters
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27114aec62
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85bd506132
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@ -87,7 +87,7 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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fn main() {
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fn main() {
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println!("Main.");
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println!("Main.");
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zynq::clocks::CpuClocks::enable_ddr(1_066_000_000);
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zynq::clocks::CpuClocks::enable_ddr(1_066_666_666);
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let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read();
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let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read();
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println!("PLLs: {}", pll_status);
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println!("PLLs: {}", pll_status);
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let clocks = zynq::clocks::CpuClocks::get();
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let clocks = zynq::clocks::CpuClocks::get();
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@ -94,17 +94,17 @@ impl CpuClocks {
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/// 25.10.4 PLLs
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/// 25.10.4 PLLs
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pub fn enable_ddr(target_clock: u32) {
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pub fn enable_ddr(target_clock: u32) {
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let fdiv = (target_clock / PS_CLK).min(66) as u16;
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let fdiv = (target_clock / PS_CLK).min(66) as u16;
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let regs = slcr::RegisterBlock::new();
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_bypass_force(true)
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.pll_fdiv(fdiv)
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);
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.nth(0)
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.nth(0)
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.expect("PLL_FDIV_LOCK_PARAM")
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.expect("PLL_FDIV_LOCK_PARAM")
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.1.clone();
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.1.clone();
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slcr::RegisterBlock::unlocked(|regs| {
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regs.ddr_pll_ctrl.modify(|_, w| w
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.pll_pwrdwn(false)
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.pll_bypass_force(true)
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.pll_fdiv(fdiv)
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);
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regs.ddr_pll_cfg.write(
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regs.ddr_pll_cfg.write(
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slcr::PllCfg::zeroed()
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slcr::PllCfg::zeroed()
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.pll_res(pll_res)
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.pll_res(pll_res)
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@ -122,6 +122,7 @@ impl CpuClocks {
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.pll_bypass_force(false)
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.pll_bypass_force(false)
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.pll_bypass_qual(false)
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.pll_bypass_qual(false)
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);
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);
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});
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}
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}
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}
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}
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@ -36,7 +36,7 @@ impl DdrRam {
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// Zynq-7000 AP SoC Technical Reference Manual:
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/// 10.6.1 DDR Clock Initialization
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/// 10.6.1 DDR Clock Initialization
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fn clock_setup(clocks: &CpuClocks) {
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fn clock_setup(clocks: &CpuClocks) {
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CpuClocks::enable_ddr(1_066_000_000);
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CpuClocks::enable_ddr(1_066_666_666);
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2;
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@ -181,14 +181,16 @@ impl DdrRam {
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// TODO: move into trait
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// TODO: move into trait
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pub fn ptr(&mut self) -> *mut u8 {
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pub fn ptr(&mut self) -> *mut u8 {
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// 0x0010_0000 as *mut _
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0x0010_0000 as *mut _
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0x0020_0000 as *mut _
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}
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}
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pub fn size(&self) -> usize {
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pub fn size(&self) -> usize {
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// #[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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// 1024 * 1024 * 1024
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let megabytes = 1024;
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4 * 1024 * 1024
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#[cfg(feature = "target_cora_z7_10")]
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let megabytes = 512;
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megabytes * 1024 * 1024
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}
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}
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pub fn memtest(&mut self) {
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pub fn memtest(&mut self) {
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