forked from M-Labs/zynq-rs
zynq::flash: add missing config bits to enable addressing mode
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a199a5dc7d
commit
5642feb824
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@ -1,5 +1,6 @@
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//! Quad-SPI Flash Controller
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//! Quad-SPI Flash Controller
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use core::marker::PhantomData;
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use crate::regs::{RegisterW, RegisterRW};
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use crate::regs::{RegisterW, RegisterRW};
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use super::slcr;
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use super::slcr;
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use super::clocks::CpuClocks;
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use super::clocks::CpuClocks;
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@ -8,23 +9,25 @@ pub mod regs;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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const FLASH_BAUD_RATE: u32 = 50_000_000;
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pub struct LinearAddressing;
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/// Flash Interface Driver
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/// Flash Interface Driver
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///
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///
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/// For 2x Spansion S25FL128SAGMFIR01
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/// For 2x Spansion S25FL128SAGMFIR01
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pub struct Flash {
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pub struct Flash<MODE> {
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regs: &'static mut regs::RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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_mode: PhantomData<MODE>,
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}
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}
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impl Flash {
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impl Flash<()> {
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pub fn new(clock: u32) -> Self {
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pub fn new(clock: u32) -> Self {
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Self::enable_clocks(clock);
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Self::enable_clocks(clock);
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Self::setup_signals();
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Self::setup_signals();
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Self::reset();
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Self::reset();
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let regs = regs::RegisterBlock::qspi();
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let regs = regs::RegisterBlock::qspi();
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let mut flash = Flash { regs };
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let mut flash = Flash { regs, _mode: PhantomData };
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flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
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flash.configure((FLASH_BAUD_RATE - 1 + clock) / FLASH_BAUD_RATE);
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flash.setup_linear_addressing_mode();
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flash
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flash
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}
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}
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@ -106,25 +109,40 @@ impl Flash {
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baud_rate_div += 1;
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baud_rate_div += 1;
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}
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}
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self.regs.config.modify(|_, w| w
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self.regs.config.write(regs::Config::zeroed()
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.baud_rate_div(baud_rate_div as u8)
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.baud_rate_div(baud_rate_div as u8)
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.mode_sel(true)
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.mode_sel(true)
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.leg_flsh(true)
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.leg_flsh(true)
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.endian(false)
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.fifo_width(0b11)
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.fifo_width(0b11)
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);
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);
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}
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}
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fn setup_linear_addressing_mode(&mut self) {
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pub fn linear_addressing_mode(self) -> Flash<LinearAddressing> {
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self.regs.lqspi_cfg.modify(|_, w| w
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// Set manual start enable to auto mode.
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// Assert the chip select.
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self.regs.config.modify(|_, w| w
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.man_start_en(false)
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.pcs(false)
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);
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self.regs.lqspi_cfg.write(regs::LqspiCfg::zeroed()
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.inst_code(0x3)
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.inst_code(0x3)
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.u_page(false)
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.u_page(false)
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.sep_bus(false)
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.sep_bus(false)
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.two_mem(false)
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.two_mem(false)
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.lq_mode(true)
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.lq_mode(true)
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);
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);
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self.regs.enable.modify(|_, w| w.spi_en(true));
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Flash {
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regs: self.regs,
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_mode: PhantomData,
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}
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}
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}
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}
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impl Flash<LinearAddressing> {
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pub fn ptr<T>(&mut self) -> *mut T {
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pub fn ptr<T>(&mut self) -> *mut T {
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0xFC00_0000 as *mut _
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0xFC00_0000 as *mut _
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}
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}
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@ -9,7 +9,7 @@ pub struct RegisterBlock {
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pub intr_en: RW<u32>,
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pub intr_en: RW<u32>,
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pub intr_dis: RW<u32>,
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pub intr_dis: RW<u32>,
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pub intr_mask: RO<u32>,
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pub intr_mask: RO<u32>,
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pub enable: RW<u32>,
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pub enable: Enable,
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pub delay: RW<u32>,
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pub delay: RW<u32>,
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pub txd0: WO<u32>,
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pub txd0: WO<u32>,
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pub rx_data: RO<u32>,
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pub rx_data: RO<u32>,
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@ -77,6 +77,9 @@ register_bit!(config,
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/// false: legacy SPI mode, true: Flash memory interface mode
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/// false: legacy SPI mode, true: Flash memory interface mode
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leg_flsh, 31);
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leg_flsh, 31);
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register!(enable, Enable, RW, u32);
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register_bit!(enable, spi_en, 0);
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register!(lqspi_cfg, LqspiCfg, RW, u32);
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register!(lqspi_cfg, LqspiCfg, RW, u32);
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register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
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register_bits!(lqspi_cfg, inst_code, u8, 0, 7);
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register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10);
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register_bits!(lqspi_cfg, dummy_byte, u8, 8, 10);
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