forked from M-Labs/zynq-rs
regs macros
This commit is contained in:
parent
9b414e2408
commit
55957eea09
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@ -7,6 +7,7 @@
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use panic_abort as _;
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use r0::zero_bss;
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mod regs;
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mod cortex_a9;
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mod slcr;
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mod uart;
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@ -0,0 +1,108 @@
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//! Interface to peripheral registers akin to the code that svd2rust
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//! generates.
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use volatile_register::{RO, WO, RW};
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use bit_field::BitField;
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pub trait Register {
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type R;
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type W;
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fn read(&self) -> Self::R;
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fn write(&self, w: Self::W);
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&self, f: F);
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}
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#[macro_export]
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macro_rules! register {
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($mod_name: ident, $struct_name: ident, $inner: ty) => (
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#[repr(packed)]
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pub struct $struct_name {
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inner: RW<$inner>,
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}
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pub mod $mod_name {
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pub struct Read {
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pub inner: $inner,
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}
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pub struct Write {
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pub inner: $inner,
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}
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}
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impl $struct_name {
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pub fn zeroed() -> $mod_name::Write {
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$mod_name::Write { inner: 0 }
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}
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}
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impl crate::regs::Register for $struct_name {
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type R = $mod_name::Read;
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type W = $mod_name::Write;
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fn read(&self) -> Self::R {
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let inner = self.inner.read();
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$mod_name::Read { inner }
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}
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fn write(&self, w: Self::W) {
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unsafe {
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self.inner.write(w.inner);
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}
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}
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fn modify<F: FnOnce(Self::R, Self::W) -> Self::W>(&self, f: F) {
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unsafe {
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self.inner.modify(|inner| {
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f($mod_name::Read { inner }, $mod_name::Write { inner })
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.inner
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});
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}
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}
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}
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);
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}
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#[macro_export]
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macro_rules! register_bit {
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($mod_name: ident, $name: ident, $bit: expr) => (
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impl $mod_name::Read {
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fn $name(&self) -> bool {
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use bit_field::BitField;
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self.inner.get_bit($bit)
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}
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}
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impl $mod_name::Write {
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fn $name(mut self, value: bool) -> Self {
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use bit_field::BitField;
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self.inner.set_bit($bit, value);
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self
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}
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}
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);
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}
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#[macro_export]
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macro_rules! register_bits {
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($mod_name: ident, $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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impl $mod_name::Read {
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fn $name(&self) -> $type {
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use bit_field::BitField;
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self.inner.get_bits($bit_begin..=$bit_end) as $type
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}
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}
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impl $mod_name::Write {
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fn $name(mut self, value: $type) -> Self {
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use bit_field::BitField;
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self.inner.set_bits($bit_begin..=$bit_end, value.into());
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self
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}
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}
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);
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}
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59
src/slcr.rs
59
src/slcr.rs
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@ -1,13 +1,11 @@
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use core::ops::RangeInclusive;
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use volatile_register::{RO, WO, RW};
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use bit_field::BitField;
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use crate::{register, register_bit, register_bits, regs::Register};
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#[repr(packed)]
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pub struct UartClkCtrl {
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pub reg: RW<u32>,
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}
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register!(uart_clk_ctrl, UartClkCtrl, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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impl UartClkCtrl {
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const ADDR: *mut Self = 0xF8000154 as *mut _;
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@ -15,26 +13,19 @@ impl UartClkCtrl {
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unsafe { &mut *Self::ADDR }
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}
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const DIVISOR: RangeInclusive<usize> = 8..=13;
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const CLKACT1: usize = 1;
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const CLKACT0: usize = 0;
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pub fn enable_uart0(&self) {
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unsafe {
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self.reg.modify(|mut x| {
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x.set_bits(Self::DIVISOR, 0x14);
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x.set_bit(Self::CLKACT0, true);
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x
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self.modify(|_, w| {
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w.clkact0(true)
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.divisor(0x14)
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})
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}
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}
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}
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#[repr(packed)]
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pub struct UartRstCtrl {
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pub reg: RW<u32>,
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}
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register!(uart_rst_ctrl, UartRstCtrl, u32);
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register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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impl UartRstCtrl {
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const ADDR: *mut Self = 0xF8000228 as *mut _;
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@ -42,29 +33,13 @@ impl UartRstCtrl {
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unsafe { &mut *Self::ADDR }
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}
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const UART1_REF_RST: usize = 3;
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const UART0_REF_RST: usize = 2;
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const UART1_CPU1X_RST: usize = 1;
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const UART0_CPU1X_RST: usize = 0;
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pub fn reset_uart0(&self) {
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unsafe { toggle(&self.reg, Self::UART0_REF_RST); }
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self.modify(|_, w| w.uart0_ref_rst(true));
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self.modify(|_, w| w.uart0_ref_rst(false));
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}
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pub fn reset_uart1(&self) {
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unsafe { toggle(&self.reg, Self::UART1_REF_RST); }
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self.modify(|_, w| w.uart1_ref_rst(true));
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self.modify(|_, w| w.uart1_ref_rst(false));
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}
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}
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unsafe fn toggle<T: BitField + Copy>(reg: &RW<T>, bit: usize) {
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reg.modify(|x| {
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let mut x = x.clone();
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x.set_bit(bit, true);
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x
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});
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reg.modify(|x| {
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let mut x = x.clone();
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x.set_bit(bit, false);
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x
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});
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}
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@ -11,9 +11,9 @@ impl Uart {
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uart_rst_ctrl.reset_uart0();
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// TODO: Route UART 0 RxD/TxD Signals to MIO Pins
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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// d. Disable UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] bit = 0.
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart0();
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149
src/uart/regs.rs
149
src/uart/regs.rs
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@ -1,28 +1,61 @@
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use volatile_register::{RO, WO, RW};
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use bit_field::BitField;
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use crate::{register, register_bit, register_bits, regs::Register};
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#[repr(u8)]
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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}
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#[repr(packed)]
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pub struct RegisterBlock {
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pub control: RW<u32>,
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pub mode: RW<u32>,
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pub intrpt_en: RW<u32>,
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pub intrpt_dis: RW<u32>,
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pub intrpt_mask: RO<u32>,
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pub chnl_int_sts: WO<u32>,
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pub baud_rate_gen: RW<u32>,
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pub rcvr_timeout: RW<u32>,
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pub rcvr_fifo_trigger_level: RW<u32>,
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pub modem_ctrl: RW<u32>,
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pub modem_sts: RW<u32>,
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pub channel_sts: RO<u32>,
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pub tx_rx_fifo: RW<u32>,
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pub baud_rate_divider: RW<u32>,
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pub flow_delay: RW<u32>,
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pub reserved0: RO<u32>,
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pub reserved1: RO<u32>,
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pub tx_fifo_trigger_level: RW<u32>,
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control: Control,
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mode: Mode,
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intrpt_en: RW<u32>,
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intrpt_dis: RW<u32>,
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intrpt_mask: RO<u32>,
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chnl_int_sts: WO<u32>,
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baud_rate_gen: BaudRateGen,
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rcvr_timeout: RW<u32>,
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rcvr_fifo_trigger_level: RW<u32>,
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modem_ctrl: RW<u32>,
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modem_sts: RW<u32>,
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channel_sts: ChannelSts,
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tx_rx_fifo: TxRxFifo,
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baud_rate_divider: BaudRateDiv,
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flow_delay: RW<u32>,
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reserved0: RO<u32>,
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reserved1: RO<u32>,
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tx_fifo_trigger_level: RW<u32>,
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}
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register!(control, Control, u32);
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register_bit!(control, rxrst, 0);
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register_bit!(control, txrst, 1);
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register_bit!(control, rxen, 2);
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register_bit!(control, rxdis, 3);
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register_bit!(control, txen, 4);
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register_bit!(control, txdis, 5);
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register!(mode, Mode, u32);
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register_bits!(mode, par, u8, 3, 5);
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register!(baud_rate_gen, BaudRateGen, u32);
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register_bits!(baud_rate_gen, cd, u16, 0, 15);
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register!(channel_sts, ChannelSts, u32);
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register_bit!(channel_sts, txfull, 4);
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register!(tx_rx_fifo, TxRxFifo, u32);
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register_bits!(tx_rx_fifo, data, u32, 0, 31);
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register!(baud_rate_div, BaudRateDiv, u32);
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register_bits!(baud_rate_div, bdiv, u8, 0, 7);
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impl RegisterBlock {
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const UART0: *mut Self = 0xE0000000 as *mut _;
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const UART1: *mut Self = 0xE0001000 as *mut _;
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@ -36,90 +69,74 @@ impl RegisterBlock {
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}
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pub fn configure(&self) {
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unsafe {
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// Confiugre UART character frame
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// * Disable clock-divider
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// * 8-bit
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// * no parity
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// * 1 stop bit
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// * Normal channel mode
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self.mode.write(0x20);
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// * no parity
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let parity_mode = ParityMode::ForceTo0;
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self.mode.write(Mode::zeroed().par(parity_mode as u8));
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// Configure the Buad Rate
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// Configure the Baud Rate
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self.disable_rx();
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self.disable_tx();
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// 9,600 baud
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self.baud_rate_gen.write(651);
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self.baud_rate_divider.write(7);
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self.baud_rate_gen.write(BaudRateGen::zeroed().cd(651));
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self.baud_rate_divider.write(BaudRateDiv::zeroed().bdiv(7));
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self.reset_rx();
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self.reset_tx();
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self.enable_rx();
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self.enable_tx();
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}
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pub fn write_byte(&self, value: u8) {
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self.tx_rx_fifo.write(TxRxFifo::zeroed().data(value.into()));
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}
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pub unsafe fn write_byte(&self, value: u8) {
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self.tx_rx_fifo.write(value.into());
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}
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const CONTROL_RXEN: usize = 2;
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const CONTROL_RXDIS: usize = 3;
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const CONTROL_TXEN: usize = 4;
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const CONTROL_TXDIS: usize = 5;
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const CONTROL_TXRST: usize = 1;
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const CONTROL_RXRST: usize = 0;
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unsafe fn disable_rx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_RXEN, false);
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x.set_bit(Self::CONTROL_RXDIS, true);
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x
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fn disable_rx(&self) {
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self.control.modify(|_, w| {
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w.rxen(false)
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.rxdis(true)
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})
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}
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unsafe fn disable_tx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_TXEN, false);
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x.set_bit(Self::CONTROL_TXDIS, true);
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x
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fn disable_tx(&self) {
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self.control.modify(|_, w| {
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w.txen(false)
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.txdis(true)
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})
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}
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unsafe fn enable_rx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_RXEN, true);
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x.set_bit(Self::CONTROL_RXDIS, false);
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x
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fn enable_rx(&self) {
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self.control.modify(|_, w| {
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w.rxen(true)
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.rxdis(false)
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})
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}
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unsafe fn enable_tx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_TXEN, true);
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x.set_bit(Self::CONTROL_TXDIS, false);
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x
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fn enable_tx(&self) {
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self.control.modify(|_, w| {
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w.txen(true)
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.txdis(false)
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})
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}
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unsafe fn reset_rx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_RXRST, true);
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x
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fn reset_rx(&self) {
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self.control.modify(|_, w| {
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w.rxrst(true)
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})
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}
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unsafe fn reset_tx(&self) {
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self.control.modify(|mut x| {
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x.set_bit(Self::CONTROL_TXRST, true);
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x
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fn reset_tx(&self) {
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self.control.modify(|_, w| {
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w.txrst(true)
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})
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}
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const CHANNEL_STS_TXFULL: usize = 4;
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pub fn tx_fifo_full(&self) -> bool {
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self.channel_sts.read().get_bit(Self::CHANNEL_STS_TXFULL)
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self.channel_sts.read().txfull()
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}
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}
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