forked from M-Labs/zynq-rs
main: start_core1
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11
src/boot.rs
11
src/boot.rs
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@ -101,3 +101,14 @@ fn l1_cache_init() {
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// way.
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// way.
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dciall();
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dciall();
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}
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}
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pub fn start_core1<T: AsMut<[u32]>>(mut stack: T) {
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let stack = stack.as_mut();
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let stack_start = &mut stack[stack.len() - 1];
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unsafe {
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CORE1_STACK = stack_start as *mut _ as u32;
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}
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// wake up core1
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asm::sev();
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}
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@ -36,6 +36,10 @@ pub fn main() {
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ddr.memtest();
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ddr.memtest();
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ram::init_alloc(&mut ddr);
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ram::init_alloc(&mut ddr);
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let core1_stack = vec![0; 2048];
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println!("{} bytes stack for core1", core1_stack.len());
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boot::start_core1(core1_stack);
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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println!("Eth on");
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