2019-05-05 20:56:23 +08:00
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#![no_std]
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#![no_main]
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#![feature(asm)]
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2019-05-31 02:30:19 +08:00
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#![feature(global_asm)]
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2019-05-05 20:56:23 +08:00
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#![feature(naked_functions)]
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2019-06-09 07:00:58 +08:00
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#![feature(compiler_builtins_lib)]
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2019-06-17 09:32:10 +08:00
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#![feature(never_type)]
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2019-05-05 20:56:23 +08:00
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2019-06-10 02:10:41 +08:00
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use core::mem::uninitialized;
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2019-05-07 22:45:31 +08:00
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2019-05-05 20:56:23 +08:00
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use r0::zero_bss;
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2019-06-09 07:00:58 +08:00
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use compiler_builtins as _;
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2019-05-05 20:56:23 +08:00
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2019-05-07 05:56:53 +08:00
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mod regs;
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2019-05-05 20:56:23 +08:00
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mod cortex_a9;
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mod slcr;
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mod uart;
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2019-06-20 06:30:18 +08:00
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mod stdio;
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2019-05-08 01:28:33 +08:00
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mod eth;
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2019-05-05 20:56:23 +08:00
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2019-06-12 06:20:23 +08:00
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use crate::regs::{RegisterR, RegisterW};
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2019-06-17 09:32:10 +08:00
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use crate::cortex_a9::{asm, regs::*, mmu};
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2019-05-24 01:05:06 +08:00
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2019-05-05 20:56:23 +08:00
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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2019-05-27 07:44:24 +08:00
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static mut __stack_start: u32;
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2019-05-05 20:56:23 +08:00
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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2019-06-12 06:20:23 +08:00
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match MPIDR.read() & CORE_MASK {
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2019-05-05 20:56:23 +08:00
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0 => {
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2019-06-12 06:20:23 +08:00
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SP.write(&mut __stack_start as *mut _ as u32);
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2019-05-20 07:21:22 +08:00
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boot_core0();
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2019-05-05 20:56:23 +08:00
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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2019-05-30 08:41:44 +08:00
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#[naked]
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#[inline(never)]
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2019-05-20 07:21:22 +08:00
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unsafe fn boot_core0() -> ! {
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2019-05-24 01:05:06 +08:00
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l1_cache_init();
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2019-05-20 07:21:22 +08:00
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zero_bss(&mut __bss_start, &mut __bss_end);
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2019-05-30 08:41:44 +08:00
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2019-06-18 08:22:07 +08:00
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let mmu_table = mmu::L1Table::get()
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.setup_flat_layout();
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mmu::with_mmu(mmu_table, || {
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2019-06-17 09:32:10 +08:00
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main();
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panic!("return from main");
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});
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2019-05-20 07:21:22 +08:00
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}
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2019-05-24 01:05:06 +08:00
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fn l1_cache_init() {
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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dccisw();
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}
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2019-05-05 20:56:23 +08:00
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fn main() {
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2019-06-20 06:30:18 +08:00
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println!("Main.");
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2019-06-05 05:49:06 +08:00
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2019-06-09 07:02:10 +08:00
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let mut eth = eth::Eth::default([0x0, 0x17, 0xde, 0xea, 0xbe, 0xef]);
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2019-06-20 06:30:18 +08:00
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println!("Eth on");
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2019-06-19 06:21:17 +08:00
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match eth::phy::Phy::find(&mut eth) {
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Some((addr, phy)) => {
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2019-06-20 06:30:18 +08:00
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println!("Found {} PHY at addr {}", phy.name(), addr);
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2019-06-19 06:21:17 +08:00
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}
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None => {
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use eth::phy::PhyAccess;
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for addr in 1..32 {
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match eth::phy::id::identify_phy(&mut eth, addr) {
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Some(identifier) => {
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2019-06-20 06:30:18 +08:00
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println!("phy {}: {:?}", addr, identifier);
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2019-06-19 06:21:17 +08:00
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}
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None => {}
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}
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}
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}
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2019-05-21 07:30:54 +08:00
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}
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2019-05-08 01:28:33 +08:00
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2019-06-21 06:58:18 +08:00
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let mut rx_descs: [eth::rx::DescEntry; 8] = unsafe { uninitialized() };
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let mut rx_buffers = [[0u8; 1536]; 8];
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let mut eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
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2019-06-10 02:10:41 +08:00
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2019-06-10 08:44:29 +08:00
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loop {
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match eth.recv_next() {
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2019-06-22 07:20:18 +08:00
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Ok(Some(pkt)) => {
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print!("eth: rx {} bytes", pkt.len());
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for b in pkt.iter() {
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print!(" {:02X}", b);
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}
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println!("");
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}
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Ok(None) => {}
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Err(e) => {
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println!("eth rx error: {:?}", e);
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2019-06-10 08:44:29 +08:00
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}
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}
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}
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2019-06-05 05:49:06 +08:00
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panic!("End");
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2019-05-05 20:56:23 +08:00
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}
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2019-05-28 06:28:35 +08:00
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#[panic_handler]
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fn panic(info: &core::panic::PanicInfo) -> ! {
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2019-06-20 06:30:18 +08:00
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println!("\nPanic: {}", info);
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2019-05-28 06:28:35 +08:00
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slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
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2019-05-31 06:19:20 +08:00
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loop {}
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2019-05-28 06:28:35 +08:00
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}
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2019-05-31 02:30:19 +08:00
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#[no_mangle]
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pub unsafe extern "C" fn PrefetchAbort() {
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panic!("PrefetchAbort");
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}
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#[no_mangle]
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pub unsafe extern "C" fn DataAbort() {
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panic!("DataAbort");
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}
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