Commit Graph

206 Commits

Author SHA1 Message Date
5ca2dbeec8 core/typedef: Add Type::obj_id to replace get_obj_id 2024-04-02 16:49:10 +08:00
4bb0e60981 core: Apply clippy suggestions 2024-04-01 16:46:41 +08:00
77de24ef74 core: Use BTreeMap for type variable mapping
There have been multiple instances where I had the need to iterate over
type variables, only to discover that the traversal order is arbitrary.

This commit fixes that by adding SortedMapping, which utilizes BTreeMap
internally to guarantee a traversal order. All instances of VarMap are
now refactored to use this to ensure that type variables are iterated in
 the order of its variable ID, which should be monotonically incremented
 by the unifier.
2024-03-04 23:56:04 +08:00
234a6bde2a core: Use TObj for NDArray 2024-03-01 15:41:55 +08:00
c3db6297d9 core: Add primitive definition-id list
So that we have a single ground truth for the definition IDs of
primitive types.
2024-03-01 11:29:10 +08:00
82fdb02d13 core: Extract LLVM intrinsic functions to their functions 2024-02-23 15:41:06 +08:00
49de81ef1e core: Apply clippy suggestions 2024-02-23 15:41:06 +08:00
8492503af2 core: Update cargo dependencies 2024-02-23 15:41:04 +08:00
2a922c7480 artiq: Fix source module of NDArray
Should be `numpy.typing` instead of `numpy`.
2024-01-17 10:40:08 +08:00
c395472094 core: Initial infrastructure for ndarray 2023-12-21 15:39:46 +08:00
bd792904f9 core: Add size_t to primitive store
Used for ndims in ndarray.
2023-12-21 15:20:31 +08:00
b47ac1b89b core: Minor formatting cleanup 2023-12-15 17:46:44 +08:00
a19f1065e3 meta: Refactor to use more let-else bindings 2023-12-12 16:31:14 +08:00
32746c37be core: Refactor to return errors by HashSet 2023-12-12 15:41:59 +08:00
beee3e1f7e artiq: Pass artiq builtins to NAC3 constructor 2023-12-12 11:28:03 +08:00
95d0c3c93c artiq: Rename const_generic_dummy to const_generic_marker 2023-12-12 11:23:51 +08:00
bd3d67f3d6 artiq: Apply clippy pedantic changes 2023-12-11 15:16:23 +08:00
02933753ca core: Apply clippy pedantic changes 2023-12-11 15:16:23 +08:00
a1f244834f meta: Bringup some documentation 2023-12-11 15:16:23 +08:00
d304afd333 meta: Apply clippy suggested changes 2023-12-11 15:16:23 +08:00
ef04696b02 meta: Lift return out of conditional statement 2023-12-11 15:16:23 +08:00
fd9f66b8d9 meta: Remove redundant casts and brackets 2023-12-11 15:16:23 +08:00
5182453bd9 meta: Remove redundant path prefixes 2023-12-11 15:16:23 +08:00
983f080ea7 artiq: Implement handling for const generic variables 2023-12-08 18:02:14 +08:00
c93ad152d7 core: Codegen for ellipsis expression as NotImplemented
A lot of refactoring was performed, specifically with relaxing
expression codegen to return Option in case where ellipsis are used
within a subexpression.
2023-12-08 18:00:51 +08:00
c2ab6b58ff artiq: Implement with legacy_parallel block 2023-11-04 13:42:44 +08:00
0a84f7ac31 Add CodeGenerator::gen_block and refactor to use it 2023-11-04 13:42:44 +08:00
352f70b885 artiq: Update host exception list to match possibly thrown types 2023-11-01 13:28:48 +08:00
9518d3fe14 artiq: Fix timeline not resetting upon exiting sequential block 2023-10-30 14:04:53 +08:00
cbd333ab10 artiq: Extract parallel block timeline utilities 2023-10-30 14:04:53 +08:00
65d6104d00 artiq: Improve IR value naming and add documentation 2023-10-30 14:04:53 +08:00
8373a6cb0f artiq: Use gen_block when generating "with sequential" 2023-10-30 14:04:53 +08:00
e1487ed335 cargo: Update dependencies 2023-10-20 18:11:45 +08:00
7fc2a30c14 Force single-threaded compilation if LLVM is not thread-safe 2023-10-16 15:55:10 +08:00
c7de22287e core: Fix restoration of stack address
All allocas for temporary objects are now placed in the beginning of the
function. Allocas for on-temporary objects are not modified because
these variables may appear in a loop and thus must be uniquely
represented.
2023-10-06 11:34:23 +08:00
2a38d5160e meta: Respect opt flags when performing whole-module optimization 2023-09-28 19:58:54 +08:00
31dcd2dde9 core: Use i8 for boolean variable allocation
In LLVM, i1 represents a 1-byte integer with a single valid bit; The
rest of the 7 upper bits are undefined. This causes problems when
using these variables in memory operations (e.g. memcpy/memmove as
needed by List slicing and assignment).

We fix this by treating all local boolean variables as i8 so that they
are well-defined for memory operations. Function ABIs will continue to
use i1, as memory operations cannot be directly performed on function
arguments or return types, instead they are always converted back into
local boolean variables (which are i8s anyways).

Fixes #315.
2023-09-25 15:42:07 +08:00
6dfc43c8b0 core: Add name to build_gep_and_load 2023-09-22 17:16:29 +08:00
ab2360d7a0 core: Remove emit_llvm from CodeGenLLVMOptions
We instead output an LLVM bitcode file when the option is specified on
the command-line.
2023-09-22 17:16:29 +08:00
411837cacd artiq: Specify target CPU when creating LLVM target options
We can try to optimize for the host and Cortex-A9 chips; The RISC-V
ISAs do not target specific chips, so we will fallback to using the
generic CPU.
2023-09-18 11:35:20 +08:00
048fcb0a69 core: Switch to LLVM New Pass Manager 2023-09-18 11:35:15 +08:00
676d07657a core: Add target field to CodeGenLLVMOptions
For specifying the target machine options when optimizing and linking.

This field is currently unused but will be required in a future
commit.
2023-09-18 09:46:24 +08:00
2482a1ef9b core: Add CodeGenTargetMachineOptions
Needed in a future commit.
2023-09-18 09:41:49 +08:00
eb63f2ad48 meta: Update to Rust Edition 2021 2023-09-15 10:25:50 +08:00
3993a5cf3f core: Add LLVM options to WorkerRegistry 2023-09-12 10:57:05 +08:00
f1b0e05b3d core: Rename IR variables
Because it is unclear which variables are expressions and
subexpressions, all variables which are previously anonymous are named
using (1) the control flow statement if available, (2) the possible name
of the variable as inferred from the variable name in Rust, and (3) the
"addr" prefix to indicate that the values are pointers. These three
strings are joint together using '.', forming "for.i.addr" for instance.
2023-09-06 14:02:15 +08:00
ff23968544 core: Add name parameter to gen_{var_alloc,store_target}
This allows variables in the IR to be assigned a custom name as opposed
to names with a default prefix.
2023-09-06 11:00:02 +08:00
d37287a33d Cargo: Update dependencies 2023-09-04 10:43:57 +08:00
aead36f0fd update dependencies 2023-03-08 15:19:09 +08:00
c1c45373a6 update dependencies 2023-01-12 19:31:03 +08:00