Sebastien Bourdeauducq d2f2415b50 analyzer: use CRI and connect at RTIO core ... This causes DMA events to be included in analyzer traces.		2017-03-02 18:47:56 +08:00
..
phy	ad9xxx -> ad9_dds	2017-01-04 11:34:52 +01:00
__init__.py	rtio: export DMA and CRIInterconnectShared	2016-12-01 16:30:29 +08:00
analyzer.py	analyzer: use CRI and connect at RTIO core	2017-03-02 18:47:56 +08:00
cdc.py	adapt to migen/misoc changes	2016-10-31 00:53:01 +08:00
core.py	rtio: use same reset for counter_rtio whatever the interface delay is	2016-12-15 09:28:13 +08:00
cri.py	perform RTIO init on comms CPU side	2016-12-09 14:16:55 +08:00
dma.py	rtio: always read full DMA sequence	2016-12-06 01:05:47 +08:00
moninj.py	moninj: do not require a rsys clock domain	2017-02-20 15:52:48 +08:00
rtlink.py	rtio: add support for latency compensation in phy	2016-12-14 19:16:07 +01:00