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rtio: always read full DMA sequence

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This commit is contained in:
Sebastien Bourdeauducq 2016-12-06 01:05:47 +08:00
parent c413d95b49
commit f3c50a37ca
1 changed files with 2 additions and 2 deletions
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4
artiq/gateware/rtio/dma.py
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@ -350,12 +350,12 @@ class DMA(Module):
self.submodules += fsm
fsm.act("IDLE",
If(self.enable.re & self.enable.r, NextState("FLOWING"))
If(self.enable.re, NextState("FLOWING"))
)
fsm.act("FLOWING",
self.enable.w.eq(1),
flow_enable.eq(1),
If(self.slicer.end_marker_found | (self.enable.re & ~self.enable.r),
If(self.slicer.end_marker_found,
NextState("FLUSH")
)
)