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artiq/artiq/gateware/rtio/phy
Sebastien Bourdeauducq cf9cf0ab6f ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
..
__init__.py rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
ad53xx_monitor.py ad53xx: port monitor, moninj dashboard, kc705 target 2018-03-24 16:04:02 +01:00
dds.py rtio/dds: use write-only RT2WB 2018-11-26 07:38:15 +08:00
edge_counter.py Add gateware input event counter 2019-01-15 10:55:07 +00:00
fastino.py fastino: use fastlink 2020-08-22 11:56:23 +00:00
fastlink.py fastlink: fix fastino style link 2020-10-18 20:43:21 +00:00
grabber.py grabber: remove unused code 2019-09-20 15:26:12 +02:00
phaser.py phaser: new multidds 2020-09-16 14:06:38 +00:00
sawg.py sawg: don't enable_replace for Config 2017-06-28 20:31:40 +02:00
servo.py gateware/suservo: Sign-extend data on RTIO read-back 2019-06-14 23:46:16 +01:00
spi2.py spi2: reset configuration in rio_phy 2018-03-07 14:42:11 +00:00
ttl_serdes_7series.py ttl_serdes_7series: add dci (HP bank) support 2021-02-07 22:32:18 +08:00
ttl_serdes_generic.py ttl_serdes: detect edges on short pulses 2020-04-13 13:21:03 +02:00
ttl_serdes_ultrascale.py ttl_serdes_ultrascale: fix, add dummy dci argument 2021-02-07 22:31:46 +08:00
ttl_simple.py rtio/ttl: expose OE 2019-10-16 18:48:20 +08:00
wishbone.py rtio/wishbone: support write-only interface 2018-11-26 07:38:06 +08:00