forked from M-Labs/artiq
Robert Jördens
324660ab40
Assume that rt2wb transactions either collide and are then reported (https://github.com/m-labs/artiq/issues/308) or that they complete and the delay with which they complete does not matter. If a transaction is ack'ed with a delay because the WB core's downstream logic is busy, that may lead to a later collision with another WB transaction. |
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.. | ||
applets | ||
compiler | ||
coredevice | ||
devices | ||
frontend | ||
gateware | ||
gui | ||
language | ||
master | ||
protocols | ||
runtime | ||
sim | ||
test | ||
wavesynth | ||
__init__.py | ||
_version.py | ||
experiment.py | ||
tools.py |