occheung
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity
2,034 Commits 14 Branches 35 Tags 23 MiB
Commit Graph

2034 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq b2f720da67 gui: better state error handling 
Remains limited by issue pyqtgraph/pyqtgraph#204
 2015-08-01 19:52:13 +08:00
Sebastien Bourdeauducq 8ad88438c7 gui: save display state 2015-08-01 19:37:16 +08:00
Sebastien Bourdeauducq a64766a10d protocols/FlatFileDB: remove unneeded default_data 2015-08-01 16:49:05 +08:00
Sebastien Bourdeauducq 00cae1c23a gui: save dock area state 2015-08-01 16:48:44 +08:00
Sebastien Bourdeauducq 9e24b56099 gui: add state manager 2015-08-01 16:48:27 +08:00
Sebastien Bourdeauducq 4a7a4acf07 conda: remove unnecessary pixman package 2015-08-01 00:16:26 +08:00
Sebastien Bourdeauducq 9b0ed344ed runtime/Makefile: WA for more pesky travis/miniconda misbehavior 2015-07-31 19:29:34 +08:00
Sebastien Bourdeauducq 89343ae276 examples/speed_benchmark: send 1MB in one RPC 2015-07-31 18:23:11 +08:00
whitequark 33531c2f3b Rename {kserver → net_server}.{c,h}. 2015-07-31 18:18:25 +08:00
Sebastien Bourdeauducq 8d1663394b runtime: increase lwip TCP_SND_QUEUELEN (closes #82) 2015-07-31 18:16:02 +08:00
Sebastien Bourdeauducq d02d40871e runtime: update lwip 2015-07-31 18:15:16 +08:00
Sebastien Bourdeauducq b4e1d1b074 conda/artiq: use $PYTHON 2015-07-31 15:03:54 +08:00
Sebastien Bourdeauducq a118d03ac6 even more travis debugging 2015-07-31 14:57:26 +08:00
Sebastien Bourdeauducq feb2c4d0c4 more travis debugging 2015-07-31 14:52:15 +08:00
Sebastien Bourdeauducq 36d92c72df travis: try export 2015-07-31 14:10:14 +08:00
Sebastien Bourdeauducq 53f55a7502 try to workaround travis problem 2015-07-31 14:01:39 +08:00
Sebastien Bourdeauducq f3c38005d3 i hate travis-ci 2015-07-31 13:58:28 +08:00
Sebastien Bourdeauducq 4df2001874 travis: try to use the new anaconda-client 2015-07-31 13:50:35 +08:00
whitequark 697b78ddf2 Rename {kserver → net_server}.{c,h}. 2015-07-30 13:45:57 +03:00
whitequark e8943a008c Rename compiler/{targets/__init__.py → targets.py}. 2015-07-30 10:35:04 +03:00
whitequark 1e3911ed39 Use try..finally in compiler.targets.Target.link. 2015-07-30 10:33:54 +03:00
whitequark b0185f3917 Add profiling to the performance testbench. 2015-07-29 22:23:22 +03:00
whitequark d7f9af4bb5 Fix accidentally quadratic code in compiler.ir.Function._add_name. 2015-07-29 21:36:31 +03:00
whitequark 6d8d0ff3f5 Update performance testbench to include time spent in ARTIQ. 2015-07-29 21:28:07 +03:00
whitequark 3b5d3e2b1a Add a performance measurement testbench. 2015-07-29 21:17:52 +03:00
Robert Jördens 55708e8678 pipistrello: drop bitgen_opt change (done upstream) 2015-07-29 11:45:15 -06:00
whitequark e8c107925c Implement shared object linking. 2015-07-29 20:35:16 +03:00
Sebastien Bourdeauducq 6b98f867de import DDS phase modes at the top level 2015-07-29 23:32:33 +08:00
Sebastien Bourdeauducq 1ddb19277f add speed benchmark 2015-07-29 23:29:26 +08:00
Sebastien Bourdeauducq 86fef7b53b master: do not scan experiments starting with '_' 2015-07-29 23:29:07 +08:00
Sebastien Bourdeauducq a8c13cb7de gui: fix NumberEntry min/max 2015-07-29 23:28:34 +08:00
Sebastien Bourdeauducq 1d34c06d79 rtio: detect collision errors 2015-07-29 19:43:35 +08:00
Sebastien Bourdeauducq b548d50a2f test/coredevice: use ttl_out for PulseRate (loop is less available) 2015-07-29 19:42:43 +08:00
whitequark 2cd25f85bf Rename artiq.compiler.testbench.{module → signature}. 2015-07-29 14:32:34 +03:00
whitequark 3378dd57b8 Fold llvmlite patches into m-labs/llvmlite repository. 2015-07-29 13:54:00 +03:00
whitequark fd46d8b11e Merge branch 'master' into new-py2llvm 2015-07-29 12:52:19 +03:00
whitequark c40ae9dbd3 MiSoC is not built with -fPIC anymore, remove support code for that. 2015-07-29 12:40:46 +03:00
Robert Jördens ebbbdcf194 examples/tdr: cleanup 2015-07-28 23:30:26 -06:00
Robert Jördens 278570faf6 examples: add TDR toy example 2015-07-28 21:36:10 -06:00
Sebastien Bourdeauducq 90368415a6 ttl: remove timestamp function 
The general idea is that functions that work with absolute timestamps exist only in machine units versions, to help prevent floating point losses of precision. Time differences should be computed in machine units and then converted, e.g. mu_to_seconds(t2-t1).

This function would have had problems after ~50 days of running the device.
 2015-07-29 11:11:16 +08:00
Robert Jördens 2640a57af3 test/coredevice: let output() settle longer 2015-07-28 16:20:05 -06:00
Robert Jördens 5f5227f01f ttl: add timestamp() 2015-07-28 16:20:05 -06:00
Robert Jördens e95b66f114 ttl: remove spurious _mu 2015-07-28 16:20:05 -06:00
whitequark b179430f6b Specify correct llvmlite branch in installation instructions. 2015-07-28 23:43:07 +03:00
Robert Jördens 67715f0d2e pipistrello: only put serdes on the lower ttls 
this setup is getting a bit power hungry.

pmt0, 1 (rtio channels 0, 1): 4x in and out
ttl0, 1 (rtio channels 2, 3): 4x out
ttl2 (rtio channel 4): 8x out
 2015-07-28 12:54:31 -06:00
Robert Jördens fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
Robert Jördens 9dfbf07743 pipistrello: use 4x serdes for rtio ttl 
pipistrello: do not wait for lock on startup

LCK_cycle:6 was added in 6a412f796e1 (mibuild). It waits for _all_
DCM and PLLs to lock (probably irrespective of STARTUP_WAIT).
 2015-07-28 12:54:27 -06:00
Sebastien Bourdeauducq 8e391e2661 kc705: generate 10MHz clock on GPIO SMA 
For SynthNV and input tests.
 2015-07-28 18:56:47 +08:00
Robert Jördens 1809a70f5c Revert "pipistrello: use 4x serdes for rtio ttl" 
This reverts commit 8e92cc91f5.

Broken. Will revisit.
 2015-07-27 23:39:35 -06:00
Robert Jördens f0a7078336 Revert "rtiocrg.c: pipistrello also has pll_reset" 
This reverts commit bdee914828.
 2015-07-27 22:18:45 -06:00