16 Commits

Author	SHA1	Message	Date
Robert Jordens	f988ec318e	pipistrello: fix csrs, make AMP default	2015-04-14 21:10:07 -06:00
Robert Jordens	70916aa0c5	pipistrello: tig _all_ async paths, add timing interference report	2015-04-14 18:18:48 -06:00
Robert Jordens	066adbdeac	pipistrello: timing report	2015-04-14 18:18:16 -06:00
Robert Jordens	6217cf5392	pipistrello: basesoc, cleanup	2015-04-14 18:18:16 -06:00
Sebastien Bourdeauducq	4c10182c9f	rtio: refactor, use rtlink	2015-04-14 19:44:45 +08:00
Sebastien Bourdeauducq	c0f1708c20	targets/pipstrello: fix mem_map	2015-04-14 19:34:14 +08:00
Florent Kermarrec	24b2bd7b6f	soc/targets: use mem_map, fix addressing conflict on UP between ethernet and dds	2015-04-11 21:32:11 +08:00
Sebastien Bourdeauducq	44304a33b2	soc,runtime: define RTIO FUD channel number in targets	2015-04-09 00:35:11 +08:00
Sebastien Bourdeauducq	7e591bb1c7	targets: use _Peripherals/UP/AMP class names, share QC1 IO defs	2015-04-07 00:07:53 +08:00
Robert Jordens	ef375b5c9c	pipistrello: add double-cpu	2015-04-04 20:52:08 -06:00
Robert Jordens	afc3982555	pipistrello: refactor single-cpu	2015-04-04 20:51:47 -06:00
Robert Jordens	0ae4492077	pipistrello: use mem_decoder	2015-04-04 20:51:47 -06:00
Robert Jordens	e50661dac4	pipistrello: fix dcm parameters, move leds, fix names	2015-04-04 20:51:47 -06:00
Florent Kermarrec	2995f0a705	remove use of _r prefix on CSRs	2015-04-02 18:30:44 +08:00
Sebastien Bourdeauducq	88a1707ef9	soc: use new location of gpio module	2015-04-02 17:19:00 +08:00
Robert Jordens	fdca0a71ff	add ARTIQMidiSoC based on pipistrello	2015-03-19 11:37:15 -06:00