forked from M-Labs/artiq
targets: use _Peripherals/UP/AMP class names, share QC1 IO defs
This commit is contained in:
parent
1ed60e0829
commit
7e591bb1c7
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@ -0,0 +1,82 @@
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from mibuild.generic_platform import *
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papilio_adapter_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")), # PMT2
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
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("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
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("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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fmc_adapter_io = [
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("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
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("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
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"LPC:LA05_N LPC:LA15_N")),
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Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
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"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
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"LPC:LA17_CC_N")),
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Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
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"LPC:LA13_N")),
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Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
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Subsignal("fud_n", Pins("LPC:LA14_P")),
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Subsignal("wr_n", Pins("LPC:LA04_P")),
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Subsignal("rd_n", Pins("LPC:LA02_N")),
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Subsignal("rst_n", Pins("LPC:LA12_P")),
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IOStandard("LVTTL")),
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]
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@ -7,47 +7,7 @@ from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from targets.kc705 import BaseSoC
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from artiq.gateware import amp, rtio, ad9858
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_tester_io = [
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("pmt", 0, Pins("LPC:LA20_N"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:LA24_P"), IOStandard("LVTTL")),
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("ttl", 0, Pins("LPC:LA21_P"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA25_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA21_N"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA25_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA22_P"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA22_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("LPC:LA11_P"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA04_N LPC:LA14_N LPC:LA05_P LPC:LA15_P "
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"LPC:LA05_N LPC:LA15_N")),
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Subsignal("d", Pins("LPC:LA06_P LPC:LA16_P LPC:LA06_N LPC:LA16_N "
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"LPC:LA07_P LPC:LA17_CC_P LPC:LA07_N "
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"LPC:LA17_CC_N")),
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Subsignal("sel", Pins("LPC:LA12_N LPC:LA03_P LPC:LA13_P LPC:LA03_N "
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"LPC:LA13_N")),
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Subsignal("p", Pins("LPC:LA11_N LPC:LA02_P")),
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Subsignal("fud_n", Pins("LPC:LA14_P")),
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Subsignal("wr_n", Pins("LPC:LA04_P")),
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Subsignal("rd_n", Pins("LPC:LA02_N")),
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Subsignal("rst_n", Pins("LPC:LA12_P")),
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IOStandard("LVTTL")),
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]
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from artiq.gateware import amp, rtio, ad9858, nist_qc1
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class _RTIOCRG(Module, AutoCSR):
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@ -68,7 +28,7 @@ class _RTIOCRG(Module, AutoCSR):
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o_O=self.cd_rtio.clk)
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class _ARTIQSoCPeripherals(BaseSoC):
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class _Peripherals(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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@ -78,7 +38,7 @@ class _ARTIQSoCPeripherals(BaseSoC):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform,
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cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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platform.add_extension(nist_qc1.fmc_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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@ -107,9 +67,9 @@ class _ARTIQSoCPeripherals(BaseSoC):
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self.comb += dds_pads.fud_n.eq(~fud)
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class ARTIQSoCBasic(_ARTIQSoCPeripherals):
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class UP(_Peripherals):
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def __init__(self, *args, **kwargs):
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_ARTIQSoCPeripherals.__init__(self, *args, **kwargs)
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_Peripherals.__init__(self, *args, **kwargs)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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@ -119,14 +79,14 @@ class ARTIQSoCBasic(_ARTIQSoCPeripherals):
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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class ARTIQSoC(_ARTIQSoCPeripherals):
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_ARTIQSoCPeripherals.csr_map)
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csr_map.update(_Peripherals.csr_map)
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def __init__(self, platform, *args, **kwargs):
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_ARTIQSoCPeripherals.__init__(self, platform, *args, **kwargs)
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_Peripherals.__init__(self, platform, *args, **kwargs)
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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@ -142,4 +102,4 @@ class ARTIQSoC(_ARTIQSoCPeripherals):
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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default_subtarget = ARTIQSoCBasic
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default_subtarget = UP
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@ -1,54 +1,12 @@
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from migen.fhdl.std import *
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from migen.bank.description import *
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from migen.bank import wbgen
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from mibuild.generic_platform import *
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from misoclib.com import gpio
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from misoclib.soc import mem_decoder
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from targets.pipistrello import BaseSoC
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from artiq.gateware import amp, rtio, ad9858
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_tester_io = [
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("ext_led", 0, Pins("B:7"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")),
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("dds_clock", 0, Pins("C:15"), IOStandard("LVTTL")),
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl", 9, Pins("C:2"), IOStandard("LVTTL")),
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("ttl", 10, Pins("C:1"), IOStandard("LVTTL")),
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("ttl", 11, Pins("C:0"), IOStandard("LVTTL")),
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("ttl", 12, Pins("B:4"), IOStandard("LVTTL")),
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("ttl", 13, Pins("A:11"), IOStandard("LVTTL")),
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("ttl", 14, Pins("B:5"), IOStandard("LVTTL")),
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("ttl", 15, Pins("A:10"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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from artiq.gateware import amp, rtio, ad9858, nist_qc1
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class _RTIOCRG(Module, AutoCSR):
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@ -87,7 +45,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
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""", rtio_clk=rtio_internal_clk)
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class _QcAdapterBase(BaseSoC):
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class _Peripherals(BaseSoC):
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csr_map = {
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"rtio": None, # mapped on Wishbone instead
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"rtiocrg": 13
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@ -96,7 +54,7 @@ class _QcAdapterBase(BaseSoC):
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def __init__(self, platform, cpu_type="or1k", **kwargs):
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BaseSoC.__init__(self, platform, cpu_type=cpu_type, **kwargs)
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platform.add_extension(_tester_io)
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platform.add_extension(nist_qc1.papilio_adapter_io)
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self.submodules.leds = gpio.GPIOOut(Cat(
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platform.request("user_led", 0),
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@ -128,9 +86,9 @@ class _QcAdapterBase(BaseSoC):
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self.comb += dds_pads.fud_n.eq(~fud)
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class Single(_QcAdapterBase):
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class UP(_Peripherals):
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def __init__(self, platform, **kwargs):
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_QcAdapterBase.__init__(self, platform, **kwargs)
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_Peripherals.__init__(self, platform, **kwargs)
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rtio_csrs = self.rtio.get_csrs()
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self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
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@ -140,14 +98,14 @@ class Single(_QcAdapterBase):
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self.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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class Double(_QcAdapterBase):
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class AMP(_Peripherals):
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csr_map = {
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"kernel_cpu": 14
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}
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csr_map.update(_QcAdapterBase.csr_map)
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csr_map.update(_Peripherals.csr_map)
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def __init__(self, platform, *args, **kwargs):
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_QcAdapterBase.__init__(self, platform, **kwargs)
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_Peripherals.__init__(self, platform, **kwargs)
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self.submodules.kernel_cpu = amp.KernelCPU(
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platform, self.sdram.crossbar.get_master())
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@ -163,4 +121,4 @@ class Double(_QcAdapterBase):
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self.kernel_cpu.add_wb_slave(mem_decoder(0xb0000000), self.dds.bus)
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default_subtarget = Single
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default_subtarget = UP
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@ -7,40 +7,7 @@ from misoclib.com import gpio
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from misoclib.mem.sdram.core.minicon import MiniconSettings
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from targets.ppro import BaseSoC
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from artiq.gateware import rtio, ad9858
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_tester_io = [
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("user_led", 1, Pins("B:7"), IOStandard("LVTTL")),
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("pmt", 0, Pins("C:13"), IOStandard("LVTTL")),
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("pmt", 1, Pins("C:14"), IOStandard("LVTTL")),
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("xtrig", 0, Pins("C:12"), IOStandard("LVTTL")), # used for DDS clock
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("ttl", 0, Pins("C:11"), IOStandard("LVTTL")),
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("ttl", 1, Pins("C:10"), IOStandard("LVTTL")),
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("ttl", 2, Pins("C:9"), IOStandard("LVTTL")),
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("ttl", 3, Pins("C:8"), IOStandard("LVTTL")),
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("ttl", 4, Pins("C:7"), IOStandard("LVTTL")),
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("ttl", 5, Pins("C:6"), IOStandard("LVTTL")),
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("ttl", 6, Pins("C:5"), IOStandard("LVTTL")),
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("ttl", 7, Pins("C:4"), IOStandard("LVTTL")),
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("ttl_l_tx_en", 0, Pins("A:9"), IOStandard("LVTTL")),
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("ttl", 8, Pins("C:3"), IOStandard("LVTTL")),
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("ttl_h_tx_en", 0, Pins("B:6"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("A:5 B:10 A:6 B:9 A:7 B:8")),
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Subsignal("d", Pins("A:12 B:3 A:13 B:2 A:14 B:1 A:15 B:0")),
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Subsignal("sel", Pins("A:2 B:14 A:1 B:15 A:0")),
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Subsignal("p", Pins("A:8 B:12")),
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Subsignal("fud_n", Pins("B:11")),
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Subsignal("wr_n", Pins("A:4")),
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Subsignal("rd_n", Pins("B:13")),
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Subsignal("rst_n", Pins("A:3")),
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IOStandard("LVTTL")),
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]
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from artiq.gateware import rtio, ad9858, nist_qc1
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class _TestGen(Module):
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@ -86,7 +53,7 @@ TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
|
|||
""", rtio_clk=rtio_internal_clk)
|
||||
|
||||
|
||||
class ARTIQMiniSoC(BaseSoC):
|
||||
class UP(BaseSoC):
|
||||
csr_map = {
|
||||
"rtio": None, # mapped on Wishbone instead
|
||||
"rtiocrg": 13
|
||||
|
|
@ -99,11 +66,11 @@ class ARTIQMiniSoC(BaseSoC):
|
|||
cpu_type=cpu_type,
|
||||
sdram_controller_settings=MiniconSettings(),
|
||||
**kwargs)
|
||||
platform.add_extension(_tester_io)
|
||||
platform.add_extension(nist_qc1.papilio_adapter_io)
|
||||
|
||||
self.submodules.leds = gpio.GPIOOut(Cat(
|
||||
platform.request("user_led", 0),
|
||||
platform.request("user_led", 1)))
|
||||
platform.request("ext_led", 0)))
|
||||
|
||||
fud = Signal()
|
||||
self.comb += [
|
||||
|
|
@ -135,4 +102,5 @@ class ARTIQMiniSoC(BaseSoC):
|
|||
self.add_wb_slave(lambda a: a[26:29] == 3, self.dds.bus)
|
||||
self.comb += dds_pads.fud_n.eq(~fud)
|
||||
|
||||
default_subtarget = ARTIQMiniSoC
|
||||
|
||||
default_subtarget = UP
|
||||
|
|
|
|||
Loading…
Reference in New Issue