03139808bd
[WIP] wavesynth/interpolate: wavesynth programming tools
...
* interpolate(t, v) will generate the channel data subset of a wavesynth
program
* still broken
2015-03-23 20:38:33 -06:00
6a0bc19279
pdq2/driver: document a few units
2015-03-23 20:31:37 -06:00
bba434e951
README/manual: refactor intro
2015-03-23 18:49:07 -06:00
8340516801
doc/manual: add faq (edited from artiq-log)
2015-03-23 18:49:07 -06:00
768fa21488
lda_controller: show default product type
2015-03-23 20:02:36 +01:00
bd145bbabc
use %(default) in argparse
2015-03-23 20:02:14 +01:00
b597483913
thorlabs_tcube: spelling, fix ping
2015-03-23 17:24:12 +01:00
Yann Sionneau
91336f974d
lda_controller: replace serial argument with device one
2015-03-23 17:02:39 +01:00
Yann Sionneau
2651050c83
Controller cleanups
2015-03-23 17:02:39 +01:00
b45ad9d1a3
examples/transport: adapt to new PDQ2 mediator (WIP, broken)
2015-03-22 22:31:59 +01:00
0b174085c8
pdq2/mediator: rewrite, adapt to new PDQ RPC format, support anonymous segments, support uploading to controllers
2015-03-22 22:30:59 +01:00
c18efa11b3
wavesynth: fix frame/segment terminology
2015-03-22 10:56:34 +01:00
1b7f71bda9
controllers: consistent device/simulation specification
2015-03-22 00:48:15 +01:00
7e61f66493
pdq2/mediator: get pdq devices from pdb
2015-03-22 00:24:42 +01:00
Florent Kermarrec
494c670cd2
targets/artiq_ppro: use new sdram_controller_settings parameter
2015-03-21 23:19:16 +01:00
e4a71e6e8c
Merge pull request #13 from whitequark/readme-fixes
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Improve installation instructions
2015-03-21 19:56:54 +01:00
whitequark
f26486e4cb
Improve installation instructions.
2015-03-21 17:01:09 +03:00
8cb77b0336
pdq2: rename url parameter to device and require it
2015-03-21 00:33:50 -06:00
05781699b8
pdq2: driver and unittest
...
* parses wavesynth style programs
* verified with cosimulated gateware
2015-03-21 00:29:00 -06:00
200e20fb39
worker: close devices immediately after run and before analyze
2015-03-20 12:01:34 +01:00
577754c38f
pdq2: fix argparser
2015-03-19 22:26:12 -06:00
222d0a9d37
pdq2_controller: add dump option
2015-03-19 21:38:46 -06:00
5ab3290ed4
pdq2: add refactored client code
2015-03-19 20:34:29 -06:00
fae7246f30
pdq2: merge from main pdq2 repo
2015-03-19 14:34:37 -06:00
fdca0a71ff
add ARTIQMidiSoC based on pipistrello
2015-03-19 11:37:15 -06:00
2257cfa952
wavesynth/compute_samples/: demonstrate dds clear
2015-03-15 18:13:47 +01:00
40bd101de0
wavesynth/compute_samples/SplinePhase: fix reduction
2015-03-15 18:13:09 +01:00
1d0fde7f13
wavesynth: program decoding
2015-03-15 18:05:03 +01:00
327448977c
wavesynth/compute_samples: use set_coefficients
2015-03-15 16:48:24 +01:00
0d8260af6e
wavesynth: basic sample computation
2015-03-15 16:30:07 +01:00
2b3641ac0a
db,worker: fix realtime result initialization
2015-03-13 15:12:55 +01:00
7a1d60ee15
coredevice,runtime,language: add parameters to runtime exceptions, include information with RTIO errors
2015-03-13 14:55:18 +01:00
84732a469d
coredevice/gpio: fix indentation
2015-03-13 14:31:50 +01:00
330e7e1b18
doc/manual: add note about avoiding __del__
2015-03-12 15:15:56 +01:00
0416da8634
runtime/test: implement ttlout, clksel and dds functions
2015-03-12 13:14:06 +01:00
3122623c6f
rtio: make 63-bit timestamp counter the default [soc]
2015-03-12 13:13:35 +01:00
d38014b07d
soc/runtime: import DDS/TTL tester (functions not accessible yet)
2015-03-11 22:02:19 +01:00
f158711f7e
test/worker: test watchdog in build()
2015-03-11 19:07:04 +01:00
43a05c783d
worker: split write_results action
2015-03-11 19:06:46 +01:00
4ba54ac929
test: do not close/recreate the asyncio event loop (WA for asyncio bugs when multiple tests are run)
2015-03-11 19:05:01 +01:00
e037b930d8
test: add worker unittest
2015-03-11 18:26:04 +01:00
5ca4821a29
ctlmgr: use workaround for asyncio.wait_for(process.wait()... Python bug
2015-03-11 16:48:16 +01:00
d5795fd619
master: watchdog support
...
Introduces a watchdog context manager to use in the experiment code that
terminates the process with an error if it times out. The syntax is:
with self.scheduler.watchdog(20*s):
...
Watchdogs timers are implemented by the master process (and the worker
communicates the necessary information about them) so that they can be
enforced even if the worker crashes. They can be nested arbitrarily.
During yields, all watchdog timers for the yielding worker are
suspended [TODO]. Setting up watchdogs is not supported in kernels,
however, a kernel can be called within watchdog contexts (and terminating
the worker will terminate the kernel [TODO]).
It is possible to implement a heartbeat mechanism using a watchdog, e.g.:
for i in range(...):
with self.scheduler.watchdog(...):
....
Crashes/freezes within the iterator or the loop management would not be
detected, but they should be rare enough.
2015-03-11 16:43:14 +01:00
f2134fa4b2
master,worker: split prepare/run/analyze
2015-03-09 23:34:09 +01:00
4c280d5fcc
master: use a new worker process for each experiment
2015-03-09 16:22:41 +01:00
ec1d082730
remove timeout from run_params (to be replaced by a better mechanism)
2015-03-09 10:51:32 +01:00
d95a9cac9a
move realtime result registration into dbh, simplify syntax
2015-03-08 17:27:27 +01:00
f2e3dfb848
Experiment base class, replace __artiq_unit__ with docstring
2015-03-08 15:55:30 +01:00
407477bc5a
test: add ARTIQ_NO_PERIPHERALS environment variable to disable tests requiring non-core devices
2015-03-08 11:40:50 +01:00
0f007cb1a7
language/db: remove implicit_core
2015-03-08 11:37:53 +01:00
