3bc0e32dc0
sawg: advance the timeline on Config access
...
c.f. #773 #765
2017-07-07 11:33:58 +02:00
3222f5036f
sawg: describe latency matching in detail
2017-07-06 10:06:21 +02:00
whitequark
1e2603572a
runtime: fix a bug causing sockets to get stuck in CLOSE-WAIT.
2017-07-05 16:27:36 +00:00
whitequark
86c027e9c5
artiq_flash: don't require binaries to merely restart FPGA.
2017-07-04 18:55:38 +00:00
whitequark
ee1d5dbccb
runtime: allow a much larger log buffer and avoid hacks.
2017-07-04 18:18:31 +00:00
whitequark
3ab8a4d505
aqctl_corelog: add missing script definition to setup.py.
2017-07-04 18:04:25 +00:00
whitequark
7a5fbc1622
devtool: forward port 1383 (moninj).
2017-07-04 17:54:18 +00:00
whitequark
4e5ea1bbaf
dashboard: fix a crash touching moninj without a connection.
2017-07-04 17:53:48 +00:00
2f1029c292
Revert "sawg: advance dds 1/2 by one sample group"
...
This reverts commit 8e0a1cbdc8#772
The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8
sawg: advance dds 1/2 by one sample group
...
closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad
sawg: also give offset some headroom
...
closes #771
2017-07-04 16:50:06 +02:00
60809d1cb4
conda: bump misoc (migen change)
2017-07-04 11:58:12 +02:00
78d1f0fdf6
sawg: fix PhasedAccu resets
2017-07-04 11:56:21 +02:00
Florent Kermarrec
42476c64a7
conda: bump migen (Record.connect leave_out --> keep/omit)
2017-07-04 11:26:57 +02:00
Florent Kermarrec
2910b1be5e
artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect
2017-07-04 10:48:06 +02:00
5b26e5de6c
conda: bump migen (reset_less cdc)
2017-07-02 15:41:58 +02:00
d7ad72efa2
doc: point to artiq_flash hardware selection options when writing flash storage. Closes #766
2017-07-02 10:40:52 +08:00
838127d914
rtio: break DMA timing path
2017-07-02 10:24:01 +08:00
whitequark
ea7549cfa4
compiler: coerce while condition to bool.
...
Fixes #768 .
2017-07-01 18:59:07 +00:00
911ee4a959
rtio: make pipelined logic reset_less
...
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61
dsp.fir: cleanup
2017-06-29 12:18:48 +02:00
dca662a743
dsp.fir: pipeline final systolic adder
2017-06-29 11:33:19 +02:00
32a33500c8
dsp.fir: actively cull zero delays
2017-06-29 11:24:56 +02:00
f520d4a768
rtio: undo _RelaxedAsyncResetSynchronizer
2017-06-28 22:08:15 +02:00
6fad15c532
conda: bump migen, misoc
...
* reset_less Cordic
* Signal.like() inherits more
* address decoder changes
2017-06-28 20:56:43 +02:00
3cbbcdfe96
sawg: don't enable_replace for Config
...
closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1
sawg: adapt latency to fir changes
...
closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578
dsp.accu: reset_less outputs
2017-06-28 20:04:58 +02:00
6bb994228f
dsp.fir: drop x shift
2017-06-28 19:55:15 +02:00
01847271c5
rtio: use reset_less signal for reset fanout
2017-06-28 19:43:55 +02:00
b9859cc0c3
dsp.fir: remove old/wrong comment
2017-06-28 19:21:57 +02:00
55b5b87490
fir: simplify latency compensation
...
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f
sawg: use pipeline reset
2017-06-28 19:09:39 +02:00
6418205906
dsp.fir: use pipelin-reset
2017-06-28 19:09:21 +02:00
whitequark
6a49c114c8
runtime: update smoltcp.
2017-06-28 00:27:22 +00:00
whitequark
370f22541c
runtime: update smoltcp.
2017-06-27 21:06:45 +00:00
whitequark
f36f00a83d
artiq_devtool: do not chop up the TCP stream into 1024 byte chunks.
...
This makes the smoltcp behavior quite different than without
the TCP forwarding (and can mask smoltcp issues).
2017-06-26 08:39:16 +00:00
whitequark
282f4256e0
artiq_pcap: atomically replace pcap file.
...
Otherwise this segfaults Wireshark (?!).
2017-06-26 03:22:14 +00:00
whitequark
d6f4f1f3bc
artiq_devtool, artiq_pcap: better option naming.
2017-06-26 00:00:05 +00:00
f4624e086a
conda: bump migen
2017-06-25 21:14:52 +02:00
whitequark
6061393bd0
tools: lazily import paramiko.
2017-06-25 07:17:03 +00:00
whitequark
816ec6c52f
artiq_pcap: implement.
2017-06-25 07:04:29 +00:00
whitequark
69fa9b38e0
test: actually run test_embedding.AsyncTest.
2017-06-25 05:28:32 +00:00
whitequark
31b52ff1b3
coredevice: do not desync kernel TCP stream on RPCReturnValueError.
...
And propagate the error upwards instead of trying to squeeze it
through the core device in futility.
2017-06-25 04:47:32 +00:00
whitequark
fdb24ef139
coredevice: truncate overlong exception messages.
...
If we have a really long one (megabytes) then this may exhaust
the heap of the core device and crash it.
2017-06-25 04:39:08 +00:00
whitequark
1fa8be3835
artiq_devtool: don't loop forever if core device dies.
2017-06-25 04:18:45 +00:00
whitequark
f17a6616b2
runtime: ensure management interface buffer can hold log buffer.
...
Otherwise we get weird edge cases where the network stack could try
to append to log buffer while management interface is holding
the log buffer and trying to push it out, and it's just no good.
The serialized log buffer at its maximum length is slightly longer
than 32 KiB, so we just allocate the largest possible TCP buffer
to the management interface to keep it simple.
2017-06-24 17:09:28 +00:00
whitequark
d0f72632e1
language: export TBytes and TByteArray.
2017-06-24 17:03:35 +00:00
whitequark
12357d884e
runtime: update smoltcp.
2017-06-24 16:55:59 +00:00
07f5e99140
dsp/sat_add: works after previous changes
2017-06-22 18:24:22 +02:00
